HSP50214BVIZ Intersil, HSP50214BVIZ Datasheet - Page 12

• Manufacturer Part Number: HSP50214BVIZ
• Description: IC DOWNCONVERTER 14BIT 120-MQFP
• Manufacturer: Intersil

Specifications of HSP50214BVIZ

• Function: Downconverter
• Rf Type: AMPS, CDMA, GSM, TDMA
• Package / Case: 120-MQFP, 120-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

-12dB
-18dB
-24dB
-30dB
-36dB
-42dB
-48dB
-54dB
-60dB
-66dB
-72dB
-78dB
FIGURE 10. INPUT THRESHOLD DETECTOR BIT WEIGHTING
-6dB
f
S
2
2
2
2
2
2
2
2
2
2
2
2
2
2
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
-13
†
Controlled via microprocessor interface.
2
2
2
2
2
2
2
2
2
2
2
2
2
2
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
-13
INTEGRATION_INTERVAL
IN(13:0)
INPUT_THRESHOLD
INTEGRATION_MODE
0
2
2
2
2
2
2
2
2
2
2
2
2
2
-10
-11
-12
-13
-1
-2
-3
-4
-5
-6
-7
-8
-9
12
CLKIN
-2
2
2
2
2
2
2
2
2
2
2
2
2
2
GATING
LOGIC
INPUT
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
-13
START
0
†
†
†
†
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
-10
-11
-12
-13
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
CONTINUOUS
R
G
E
|X|
COUNTER
16
0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-1
-2
-3
-4
HSP50214B
“0”
FIGURE 9.
+
ACCUMULATOR
CLKIN
The integration period counter can be set up to run
continuously or to count down and stop. Continuous integration
counter operation lets the counter run, with sampling occurring
every time the counter reaches zero. Because the processor
samples the detector read port asynchronous to the CLKIN,
data can be missed unless the status bit is monitored by the
processor to ensure that a sample is taken for every integration
count down sequence.
Additionally, in the HSP50214B, the ability to align the
start/restart of the input level detector integration period with
an external event is provided. This allows the sync signals,
which are synchronized to external events, to be used to align
all of the gain adjustments or measurements. If Control Word
27, Bit 17 is set to a logic one, the SYNCIN1 signal will cause
the input level detector to start/restart its integration period. If
Control Word 27, Bit 17 is set to a logic zero, control of the
start/restart of the input level detector integration period does
not respond to SYNCIN1.
In the count down and stop mode, the microprocessor read
commands can be synchronized to system events, such as the
start of a burst for a TDMA application. The integration counter
can be started at any time by writing to Control Word 2. At the
end of the integration period (counter = 0000), the upper 23-bits
of the accumulator are transferred to a holding register for
reading by the microprocessor. Note that it is not the restarting
of the counter (by writing to Control Word 2) that latches the
current value, but the end of the integration count. When the
accumulator results are latched, a bit is set in the Status
Register to notify the processor. Reading the most significant
byte of the 23-bits clears the status bit. See the Microprocessor
Read Section. Figure 11 illustrates a typical AGC detection
process.
+
SINGLE
32
R
E
G
R
E
G
24
ADDR(2:0)
M
U
X
8
TO
μPROC
May 1, 2007
FN4450.4