HSP50214BVCZ Intersil, HSP50214BVCZ Datasheet

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... AGC level in either parallel or serial format. Ordering Information PART NUMBER PART MARKING HSP50214BVC HSP50214BVC HSP50214BVCZ (Note) HSP50214BVCZ HSP50214BVI HSP50214BVI HSP50214BVIZ (Note) HSP50214BVIZ NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...

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Block Diagram MICROPROCESSOR READ/WRITE CONTROL C(7:0) LEVEL DETECT ORDER FILTER IN(13:0) GAIN ORDER ADJ (2:0) FILTER CARRIER COF NCO SOF CLKIN PROCCLK REFCLK 2 HSP50214B AGC LOOP FILTER TH POLYPHASE 5 FIR AND CIC HALFBAND FILTERS TH POLYPHASE 5 FIR ...

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Pinout 1 IN10 2 IN9 3 IN8 4 GND 5 IN7 IN6 8 IN5 9 IN4 10 IN3 IN2 11 12 GND 13 IN1 14 IN0 CLKIN 17 GND ENI ...

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Pin Descriptions NAME TYPE V - Positive Power Supply Voltage. CC GND - Ground. CLKIN I Input Clock. This clock should be a multiple of the input sample rate. All input section processing occurs on the rising edge of CLKIN. ...

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Pin Descriptions (Continued) NAME TYPE DATARDY O Output Strobe Signal. Active Low. Indicates when new data from the Direct Output Port Section is available. DATARDY is asserted for one PROCCLK cycle during the first clock cycle that data is available ...

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AGCGNSEL PROCCLK CLKIN GAINADJ(2:0) ENI IN(13:0) 5TH ORDER CIC LEVEL HALFBAND FILTER; MIXER DETECT DECIMATE DECIMATION FROM 4-32 TO μPROCESSOR INTERFACE COF NCO COFSYNC (CARRIER TRACKING) SOF SOFSYNC REFCLK MICROPROCESSOR READ/WRITE RD WR CONTROL ...

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Functional Description The HSP50214B Programmable Downconverter (PDC agile digital tuner designed to meet the requirements of a wide variety of communications industry standards. The PDC contains the processing functions needed to convert sampled IF signals to baseband digital ...

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The synchronous gain adjustment allows the user to measure the power of the signal at the A/D at the end of a burst, and synchronously reload ...

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Input and Processing Resolution The PDC maintains a minimum of 14-bits of processing resolution through to the output, providing over 84dB of dynamic range. The 18-bits of resolution on the internal references provide a spurious floor that is better ...

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See Figures for an interpolated input example, detailing the associated spectral results. Interpolation Example: The specifications for the interpolated input example are: CLKIN = 40MHz Input Sample Rate = 5MSPS PROCCLK = 28MHz Interpolate by 8, Decimate ...

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S S 5MHz 10MHz f’ /8 f’ 5MHz 10MHz FIGURE 6. INTERPOLATION SPECTRUM: INTERPOLATE BY 8 THE INPUT DATA WITH ZERO STUFFING; SAMPLE AT RATE R = f’s 4MHz 8MHz DECIMATE BY 10 AND CIC ...

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INPUT GATING IN(13:0) LOGIC INPUT_THRESHOLD INTEGRATION_INTERVAL START INTEGRATION_MODE CLKIN † Controlled via microprocessor interface -6dB - ...

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Typically, the average input error is read from the Input Level Detector port for use in AGC Applications. By setting the threshold to 0, however, the average value of the input signal can be read directly. The calculation is: ( ...

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The phase of the Carrier NCO can be shifted by adding a 10- bit phase offset to the MSB’s (modulo 360 the output of the phase accumulator. This phase offset control has a resolution of 0.35 o ...

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NOTE: COF loading and timing is relative to CLKIN while SOF loading and timing is relative to PROCCLK. NOTE: T can be 0, and the fastest rate is with 8-bit word width. D The assertion of the COFSYNC (or SOFSYNC) ...

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The sum of the input bits and the growth bits cannot exceed the accumulator size. This means that for a decimation of 32 and 15 input bits, the first accumulator must be ...

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...

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BANDWIDTH -20 -40 HALFBAND FILTER 5 -60 HALFBAND FILTER 4 HALFBAND FILTER 3 -80 HALFBAND FILTER 2 HALFBAND FILTER 1 -100 -120 0.125 0.25 NORMALIZED FREQUENCY (F FIGURE 18. HALFBAND FILTER FREQUENCY RESPONSE 0 ALIAS PROFILES -20 -40 ...

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COEFFICIENTS HALFBAND #1 - 0.031303406 C0 0.000000000 C1 0.281280518 C2 0.499954224 C3 0.281280518 C4 0.000000000 C5 - 0.031303406 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 NOTE: While Halfband filters are ...

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Additionally, the Programmable FIR filter provides for decimation factors, R, from 1 to 16. The processing rate of the Filter Compute Engine is PROCCLK result, the frequency of PROCCLK must exceed a minimum value to ensure that a ...

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Without gain control, a signal at -72dBFS = -12 20log ( the input would have only 4-bits of 10 resolution at the output (12-bits less than the full scale 16-bits). The potential increase in the bit ...

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AGC THRESHOLD value (Control Word 8, Bits 16-28) is shown in Table 5. Note that the MSB is always zero. The range of the AGC THRESHOLD value +3.9995. The AGC Error Detector output has the identical ...

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CONTROL WORD 9 BIT: FORMAT 16 MSB = 0 SERIAL OUT 16 MSB = 0 μP (11 MANTISSA EN 4 EXPONENT NNNN EXP IFIR 18 26 QFIR AGC MULTIPLIER/SHIFTER Controlled via microprocessor interface. † Using AGC ...

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AGC rate is ~ 0.000106 to 3.275dB/output sample time for a threshold of 1/2 scale. See the notes at the bottom of Table 9A for calculation of the AGC response times. The maximum AGC Response is given ...

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These gain error values are scaled by the programmable AGC loop gains to adjust the data path gain. The maximum slew rate is ~1.5dB per output sample. See Equation 18. In order to fully evaluate the dynamic range of the ...

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TABLE 9A. BIT WEIGHTING FOR AGC LOOP FEEDBACK PATH AGC GAIN ACCUM GAIN ERROR AGC LOOP BIT ERROR BIT FILTER GAIN POSITION INPUT WEIGHT (MANTISSA ...

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BIT WEIGHT INPUT SIN/COS MIX OUT ...

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FREQUENCY (RELATIVE TO f FIGURE 24C. POLYPHASE RESAMPLER FILTER EXPANDED RESOLUTION PASSBAND FREQUENCY RESPONSE TABLE 10. POLYPHASE AND INTERPOLATING HALFBAND FILTER MAXIMUM CLOCKING RATES RE-SAMPLER INPUT CLOCK ...

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EN EXT TIMING NCO SYNC SYNC SYNCIN2 † TIMING PHASE STROBE 5 TIMING NCO 8 + † PHASE OFFSET PHASE ACCUMULATOR REG + † ENABLE SOF MUX SOF REG REG REG SYNC SOFSYNC SOF SHIFT REG ...

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Cartesian to Polar Converter The Cartesian to Polar converter computes the magnitude and phase of the I/Q vector. The I and Q inputs are 18 bits. The converter phase output is 18-bits (truncated) with the 16 MSB’s routed to the ...

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One caveat to selecting the FIR outputs to be routed directly to the coordinate converter is that because the I/Q samples for the coordinate conversion are chosen from before the resampler, the magnitude and phase samples will not align with ...

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The Discriminator FIR filter input selections are made in Control Word 27, Bits 18 and 19. The bit definitions are: 00 Item (1) described above. 01 Item (2) described above. 1X Item (3) described above. Control Word 27, Bit 14 ...

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Data Ready Signal Assertion Rate: The assertion rate of the DATARDY signal Is the data transition rate of the A output data either [I, |r| or f]. The OUT time alignment of parallel data words available for output are as ...

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Serial Direct Output Port Mode The Serial Direct Output Port Mode offers the ability to construct two serial output data streams, SEROUTA AND SEROUTB, from 16-bit I, Q, magnitude, phase, frequency, timing error, and AGC level data words. The total ...

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SEROUTB: CONTROL WORD 19 FIELD end > I (15:0) (2’s COMP) Q (15:0) (2’s COMP) |r| (15:0) SHIFT REG (O; UNSIGNED BINARY) φ (15:0) SHIFT REG (2’s COMP) f (15:0) SHIFT REG (2’s COMP) TE SHIFT REG (15:0) (2’s COMP) ...

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Serial Output Configuration Example desired to output the I data word, followed by the Q data word, followed by the Phase data word on the SEROUTA output. Similarly desired to output the Magnitude data word ...

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DATA WORD 3 MAGNITUDE DATA WORD 3 TBD THE REMAINING CHOICES FOR THE THIRD LINK ON SEROUTB ARE: PHASE, FREQUENCY, AGC LEVEL, AND TIMING ERROR “NORMAL” 0 SERSYNC FOLLOWS LSB 0 “INVERTED” 1 “NORMAL” SERSYNC PRECEDES MSB “INVERTED” 1 LSB ...

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The FIFO mode allows the processor to service the interface only when enough samples are present in the RAM. This mode is provided so that the μProcessor does not have to service the PDC every output sample. An interrupt, INTRRPT, ...

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Figure 37 shows the interface between a 16-bit microprocessor (or other baseband processing engine) and the Buffer RAM Output Section of the Programmable Down Converter, configured for data output via the parallel outputs AOUT and BOUT. In the 16-bit microprocessor ...

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FIGURE 40A. FIFO DEPTH IS (WRITE - READ FIGURE 40B. FIFO FULL IS WHEN (WRITE - READ ...

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DUAL 16 |r| PORT 16 φ RAM 16 ƒ “SET OF WORDS” WRITE SEQUENCER ADDRESS SEQUENCER INCR INCR WR RD NEW DATA CONTROL WORD 23 WRITE A(2:0) R2, R1, R0 ADDRESS “5” A2, A1 ...

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The PDC begins to fill the buffer each time an interval number of samples have passed. The number of sample sets the PDC writes into the buffer and is programmed into bits 3-0 of Control Word 21. The number of ...

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TABLE 20. EXAMPLE PROCESSOR WRITE SEQUENCE STEP A(2:0) C(7:0) 1 000 0011 1000 Loads 38 into Master Register (7:0) on rising edge of WR. 2 001 1101 0000 Loads D0 into Master Register (15:8) on rising edge of WR. 3 ...

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TABLE 22. DEFINITION OF ADDRESS MAP (Continued) READ STATUS CODE C(2:0) TYPE READ ADDRESS A(2:0) 101 AGC Data AGC (must write to location 10 to and Timing sample) Error 000- AGC LSB (lower 8-bits of linear Control Word 3 used ...

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... PDC, refer to AN9720 [3], “Calculating the Maximum Processing Rates of the PDC”. 45 HSP50214B References For Intersil documents available on the web, see www.intersil.com/ [1] HSP50210 Data Sheet, Intersil Corporation, FN3652. [2] Cellular Radio and Personal Communications: A Book of Selected Readings, Theodore S. Rappaport, 1995 by IEEE, Inc ...

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CIC INPUT RATE S -130 FREQUENCY FIGURE 48A. CIC FILTER RESPONSE 10 -10 -30 -50 -70 -90 -110 f = CIC INPUT RATE S -130 FREQUENCY FIGURE 48C. HB5 FILTER RESPONSE ...

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Configuration Control Word Definitions Note that in the Configuration Control Register Tables, some of the available 32-bits in a Control Word are not used. Unused bits do not need to be written to the Master Register. If the destination only ...

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CONTROL WORD 1: INPUT LEVEL DETECTOR (SYNCHRONOUS TO CLKIN) BIT POSITION FUNCTION 31 Reserved 30 Integration Mode 29-14 Integration Interval 13-0 Input Threshold CONTROL WORD 2: INPUT LEVEL DETECTOR START STROBE (SYNCHRONIZED TO CLKIN) BIT POSITION FUNCTION N/A Start Input ...

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CONTROL WORD 7: HB, FIR CONFIGURATION (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION 31-22 Reserved Reserved. 21 Enable External 0- The SYNCIN2 pin has no effect on the halfband and FIR filters. Filter Sync 1- When the SYNCIN2 pin is asserted, ...

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CONTROL WORD 9: AGC CONFIGURATION 2 (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION 31-28 Reserved Reserved. 27-16 Upper Limit Maximum Gain/Minimum Signal. The upper four bits are used for exponent; the remaining bits form the mantissa in the fractional offset binary: ...

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CONTROL WORD 13: TIMING PHASE OFFSET (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION 31-8 Reserved Reserved. 7-0 Timing NCO Phase These bits are used to offset the phase of the Timing NCO. The range times the resampler ...

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CONTROL WORD 17: DISCRIMINATOR FILTER CONTROL, DISCRIMINATOR DELAY (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION 31-17 Reserved Reserved. 16-15 Phase Multiplier These bits program allow the phase output of the cartesian to polar converter to be multiplied ...

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CONTROL WORD 19: SERIAL OUTPUT ORDER (SYNCHRONIZED TO PROCCLK) (Continued) BIT POSITION FUNCTION 17-15 Link Following Q Data The serial data word, or link, following the Q data word is selected using Table 12 (see Output Section). 14-12 Link Following ...

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CONTROL WORD 20: BUFFER RAM, DIRECT PARALLEL, AND DIRECT SERIAL OUTPUT CONFIGURATION BIT POSITION FUNCTION 11-10 Q Data Serial Output (See I Data Serial Output Tag selection above). Tag Bit 9-8 Magnitude Data Serial (See I Data Serial Output Tag ...

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CONTROL WORD 25: COUNTER AND ACCUMULATOR RESET (SYNCHRONIZED TO BOTH CLKIN AND PROCCLK) BIT POSITION FUNCTION N/A Counter and A write to this address initializes the counters and accumulators for testing. Items that are reset are: Accumulator Reset Carrier NCO. ...

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CONTROL WORD 26: LOAD AGC GAIN (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION (15:12) eeee - AGC Exponent (11:5) mmmmmmm - AGC Mantissa (5:0) 000000 - Not Used CONTROL WORD 27: TEST REGISTER (SYNCHRONIZED TO CLKIN) BIT POSITION FUNCTION 31-25 Reserved ...

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CONTROL WORDS 64-95: DISCRIMINATOR COEFFICIENT REGISTERS (SYNCHRONIZED TO PROCCLK) BIT POSITION FUNCTION 31-10 Discriminator FIR The discriminator FIR coefficients are 22-bit-two’s complement. If the filter is symmetric, the coefficients Coefficient are loaded from the center coefficient at address 64 to ...

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... Thermal Information Thermal Resistance (Typical, Note 4) +0.5V MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . CC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp ±5 0°C to +70°C, Commercial; -40°C to +85°C, Industrial CC A SYMBOL TEST CONDITIONS ...

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AC Electrical Specifications PARAMETER Hold Time GAINADJ(2:0), IN(13:0), ENI, COF, COFSYNC, and SYNCIN1 from CLKIN Setup Time AGCGNSEL, SOF, MCSYNCI, SOFSYNC, and SYNCIN2 to PROCCLK Hold Time AGCGNSEL, SOF, MCSYNCI, SOFSYNC, and SYNCIN2 from PROCCLK Setup Time, A(2:0) to Rising ...

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AC Test Load Circuit SWITCH S1 OPEN FOR I NOTE: Test head capacitance. Waveforms t WRL WSA t t WSC C(0-7), A(0-2) FIGURE 49. TIMING RELATIVE 2.0V 0.8V FIGURE 51. OUTPUT RISE AND ...

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Waveforms OEAH, OEAL, 1.5V OEBH, OEBL OEBL OUTA(15:8), OUTA(7:0), 1.7V OUTB(15:8), OUTB(7:0) 1.3V FIGURE 53. OUTPUT ENABLE/DISABLE 61 HSP50214B PROCCLK AGCGNSEL, MCSYNC1 SOF, SOFSYNC, SYNCIN2 AOUT(15:0), 1.5V BOUT(15:0), DATARDY, INTRRP, MCSYNC0, t SYNCOUT, SEROUTA, OD SEROUTB SERSYNC ...

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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...