TDA6651TT/C3,118 NXP Semiconductors, TDA6651TT/C3,118 Datasheet - Page 2

• Manufacturer Part Number: TDA6651TT/C3,118
• Description: IC MXR/OSC AND SYNTH 38-TSSOP
• Manufacturer: NXP Semiconductors

Specifications of TDA6651TT/C3,118

• Function: Mixer
• Package / Case: 38-TFSOP (0.173", 4.40mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935277153118

NXP Semiconductors
2. Features
TDA6650TT_6651TT_5
Product data sheet
Five open-drain PMOS ports are included on the IC. Two of them, BS1 and BS2, are also
dedicated to the selection of the low, mid and high bands. PMOS port BS5 pin is shared
with the ADC.
The AGC detector provides a control that can be used in a tuner to set the gain of the
RF stage. Six AGC take-over points are available by software. Two programmable AGC
time constants are available for search tuning and normal tuner operation.
The local oscillator signal is fed to the fractional-N divider. The divided frequency is
compared to the comparison frequency into the fast phase detector which drives the
charge pump. The loop amplifier is also on-chip, including the high-voltage transistor to
drive directly the 33 V tuning voltage without the need to add an external transistor.
The comparison frequency is obtained from an on-chip crystal oscillator. The crystal
frequency can be output to the XTOUT pin to drive the clock input of a digital
demodulation IC.
Control data is entered via the I
select the Local Oscillator (LO) frequency, select the step frequency, program the output
ports and set the charge pump current or select the ALBC mode, enable or disable the
crystal output buffer, select the AGC take-over point and time constant and/or select a
specific test mode. A status byte concerning the AGC level detector and the ADC voltage
can be read out on the SDA line during a read operation. During a read operation, the loop
‘in-lock’ flag, the power-on reset flag and the automatic loop bandwidth control flag are
read.
The device has 4 programmable addresses. Each address can be selected by applying a
specific voltage to pin AS, enabling the use of multiple devices in the same system.
The I
description and is compatible with 5 V, 3.3 V and 2.5 V microcontrollers depending on the
voltage applied to pin BVS.
I
I
I
I
I
I
I
Single-chip 5 V mixer/oscillator and low phase noise PLL synthesizer for TV and VCR
tuners, dedicated to hybrid (digital and analog) as well as pure digital applications
(DVB-T)
Five possible step frequencies to cope with different digital terrestrial TV and
analog TV standards
Eight charge pump currents between 40 A and 600 A to reach the optimum phase
noise performance over the bands
Automatic Loop Bandwidth Control (ALBC) sets the optimum phase noise
performance for DVB-T channels
I
Five PMOS open-drain ports with 15 mA source capability for band switching and
general purpose; one of these ports is combined with a 5-step ADC
Wideband AGC detector for internal tuner AGC:
2
N
N
N
C-bus protocol compatible with 2.5 V, 3.3 V and 5 V microcontrollers:
2
C-bus is fast mode compatible, except for the timing as described in the functional
Address + 5 data bytes transmission (I
Address + 1 status byte (I
Four independent I
Rev. 05 — 10 January 2007
2
C-bus addresses.
2
C-bus; six serial bytes are required to address the device,
2
C-bus read mode)
5 V mixer/oscillator and low noise PLL synthesizer
TDA6650TT; TDA6651TT
2
C-bus write mode)
© NXP B.V. 2007. All rights reserved.
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