TDA6651TT/C3,118 NXP Semiconductors, TDA6651TT/C3,118 Datasheet - Page 13

• Manufacturer Part Number: TDA6651TT/C3,118
• Description: IC MXR/OSC AND SYNTH 38-TSSOP
• Manufacturer: NXP Semiconductors

Specifications of TDA6651TT/C3,118

• Function: Mixer
• Package / Case: 38-TFSOP (0.173", 4.40mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935277153118

NXP Semiconductors
TDA6650TT_6651TT_5
Product data sheet
8.2 Read mode; R/W = 1
Table 14.
Data can be read from the device by setting the R/W bit to 1 (see
device address has been recognized, the device generates an acknowledge pulse and the
first data byte (status byte) is transferred on the SDA line (MSB first). Data is valid on the
SDA line during a HIGH level of the SCL clock signal.
A second data byte can be read from the device if the microcontroller generates an
acknowledge on the SDA line (master acknowledge). End of transmission will occur if no
master acknowledge occurs. The device will then release the data line to allow the
microcontroller to generate a STOP condition.
Table 15.
[1]
Table 16.
LO frequency
184 MHz to 196 MHz
196 MHz to 224 MHz
224 MHz to 296 MHz
296 MHz to 380 MHz
380 MHz to 404 MHz
404 MHz to 448 MHz
448 MHz to 472 MHz
472 MHz to 484 MHz
484 MHz to 604 MHz
604 MHz to 676 MHz
676 MHz to 752 MHz
752 MHz to 868 MHz
868 MHz to 904 MHz
Name
Address byte 1
Status byte
Bit
A
POR
FL
MSB is transmitted first.
ALBC band selection and charge current setting
I
Description of read data format bits
2
C-bus read data format
Byte Bit
2
Description
acknowledge bit
power-on reset flag
in-lock flag
POR = 0, normal operation
POR = 1, power-on reset
FL = 0, not locked
FL = 1, the PLL is locked
MSB
1
POR
Rev. 05 — 10 January 2007
[1]
1
FL
5 V mixer/oscillator and low noise PLL synthesizer
Band
low
mid
mid
mid
mid
mid
mid
mid
high
high
high
high
high
0
ALBC
TDA6650TT; TDA6651TT
0
1
0
AGC
…continued
MA1
A2
Charge pump current
number
7
2
3
4
5
6
7
8
4
5
6
7
8
Table
MA0
A1
© NXP B.V. 2007. All rights reserved.
15). After the
LSB
R/W = 1 A
A0
13 of 54
ACK
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