SI4703-B17-EVB Silicon Laboratories Inc, SI4703-B17-EVB Datasheet - Page 20

• Manufacturer Part Number: SI4703-B17-EVB
• Description: BOARD EVAL SI4703 VERSION B
• Manufacturer: Silicon Laboratories Inc
• Type: Tunerr

Specifications of SI4703-B17-EVB

• Frequency: 76MHz ~ 108MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Si4703
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Si4702/03-C19
When
Si4702/03-C19, the ENABLE and DISABLE bits in
Register 02h can be used to select between powerup
and powerdown modes. When voltage is first applied to
the device, ENABLE = 0 and DISABLE = 0. Setting
ENABLE = 1 and DISABLE = 0 puts the device in
powerup mode. To power down the device, disable RDS
to prevent any unpredictable behavior (Si4703 only),
then write ENABLE and DISABLE bits to 1.
After being written to 1, both bits will be cleared as part
of the internal device powerdown sequence. To put the
device back into powerup mode, set ENABLE = 1 and
DISABLE = 0 as described above. The ENABLE bit
should never be written to a 0.
20
Select Method
Notes:
Xtal Oscillator
Xtal Oscillator
Xtal Oscillator
Xtal Oscillator
Busmode
Table 9. Selecting 2-Wire or 3-Wire Control
1. All parameters applied on rising edge of RST.
2. When selecting 2-wire mode, the user must ensure
3. GPIO3 is internally pulled down with a 1 M  resistor.
4. GPIO3 should be externally driven low, set to high-Z
5. GPIO3 should be left floating.
6. GPIO3 should be externally driven high (100 k  or
that SCLK is high during the rising edge of RST, and
stays high until the 1st start condition.
(10 M  or greater pull-up) or float.
smaller pull-up).
1
1
1
1
2
2
2
2
Interface Busmode Operation
proper
SEN SDIO GPIO1 GPIO3
NA
NA
X
X
0
1
0
1
voltages
NA
NA
X
X
0
0
0
0
are
NA
NA
X
X
X
X
0
1
applied
NA
NA
0
0
0
0
1
1
4
4
5
5
6
6
1,2,3
2
to
3-wire
2-wire
3-wire
2-wire
3-wire
2-wire
mode
Bus
NA
NA
the
Rev. 1.1
4.10. Audio Output Summation
The audio outputs LOUT and ROUT may be
capacitively summed with another device. Setting the
audio high-Z enable (AHIZEN) bit maintains a dc bias of
0.5 x V
ESD diodes from clamping to the V
response to the output swing of the other device. The
bias point is set with a 370 k resistor to V
Register 07h containing the AHIZEN bit must not be
written during the powerup sequence and only takes
effect when in powerdown and V
powerup the LOUT and ROUT pins are set to the
common mode voltage specified in Table 8, “FM
Receiver Characteristics
the state of AHIZEN. Bits 13:0 of register 07h must be
preserved as 0x0100 while in powerdown and as
0x3C04 while in powerup.
4.11. Initialization Sequence
Refer to Figure 9, “Initialization Sequence,” on page 21.
To initialize the device:
1. Supply V
2. Supply V
3. Select 2-wire or 3-wire control interface bus mode
4. Provide RCLK. Steps 3 and 4 may be reversed when using
5. Set the ENABLE bit high and the DISABLE bit low to
To power down the device:
1. (Optional) Set the AHIZEN bit high to maintain a dc bias of
2. Set the ENABLE bit high and the DISABLE bit high to
3. (Optional) Remove RCLK.
4. Remove V
1 and 2 may be reversed. Power supplies may be
sequenced in any order.
operation as described in Section 4.9. "Reset, Powerup,
and Powerdown" on page 19.
an external oscillator. Refer to AN230 when using internal
oscillator.
powerup the device. Software should wait for the powerup
time
Characteristics
normal part operation.
0.5 x V
powerdown, but preserve the states of the other bits in
Register 07h. Note that in powerup the LOUT and ROUT
pins are set to the common mode voltage specified in
Table 8 on page 12, regardless of the state of AHIZEN.
place the device in powerdown mode. Note that all register
states are maintained so long as V
RST pin is high.
IO
IO
on the LOUT and ROUT pins to prevent the
(as
A
IO
volts at the LOUT and ROUT pins while in
A
and V
while keeping the RST pin low. Note that steps
and V
specified
1,2
D
,” on page 12) before continuing with
.
D
supplies as needed.
1,2
by
,” on page 12, regardless of
Table 8,
IO
IO
IO
is supplied and the
is supplied. In
or GND rail in
“FM
IO
and GND.
Receiver