SI4703-B17-EVB Silicon Laboratories Inc, SI4703-B17-EVB Datasheet
SI4703-B17-EVB
Specifications of SI4703-B17-EVB
Related parts for SI4703-B17-EVB
SI4703-B17-EVB Summary of contents
Page 1
... V supply voltage Integrated LDO regulator allows direct connection to battery 20-pin QFN package Pb-free/RoHS compliant RDS/RBDS Processor (Si4703) Integrated crystal oscillator Portable navigation Consumer electronics Si4702/03 DSP I LOUT DAC ADC ...
Page 2
Si4702/03-C19 2 Rev. 1.1 ...
Page 3
... Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 7. Pin Descriptions: Si4702/03-C19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9. Package Markings (Top Marks 9.1. Si4702 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.2. Si4703 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.3. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10. Package Outline: Si4702/03-C19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11. PCB Land Pattern: Si4702/03-C19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Contact Information ...
Page 4
Si4702/03-C19 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Digital Supply Voltage Analog Supply Voltage Interface Supply Voltage Digital Power Supply Power-Up Rise Time Analog Power Supply Power-Up Rise Time Interface Power Supply Power-Up Rise Time Ambient Temperature Note: ...
Page 5
... Analog and digital supply currents are simultaneously adjusted based on SNR level. 5. Stereo and RDS functionality are disabled at low SNR levels. 6. RDS functionality only available for Si4703. 7. Refer to Section 4.9. "Reset, Powerup, and Powerdown" on page 19. 8. For input pins SCLK, SEN, SDIO, RST, RCLK, GPIO1, GPIO2, and GPIO3. ...
Page 6
Si4702/03-C19 Table 4. Reset Timing Characteristics (Busmode Select Method 1) Parameter RSTpulse width and GPIO3 Setup to RST SEN and SDIO Setup to RST SEN, SDIO, and GPIO3 Hold from RST Notes: 1. When selecting 2-wire Mode, the user must ...
Page 7
Table 5. Reset Timing Characteristics (Busmode Select Method 2) Parameter GPIO1 and GPIO3 Setup to RST GPIO1 and GPIO3 Hold from RST Notes: 1. When selecting 2-wire Mode, the user must ensure that a 2-wire start condition (falling edge of ...
Page 8
Si4702/03-C19 Table 6. 3-Wire Control Interface Characteristics ( 2 1 Parameter SCLK Frequency SCLK High Time SCLK Low Time SDIO Input, SEN to SCLKSetup SDIO ...
Page 9
SCLK 30 70% SEN 30% 80% SDIO A7 20% Address In Figure 4. 3-Wire Control Interface Read Timing Parameters t t HSDIO CDV t S A6-A5, R/W, A0 D15 A4-A1 ½ Cycle Bus Turnaround Rev. 1.1 Si4702/03-C19 ...
Page 10
Si4702/03-C19 Table 7. 2-Wire Control Interface Characteristics ( 2 1 Parameter SCLK Frequency SCLK Low Time SCLK High Time SCLK Input to SDIO Setup ...
Page 11
SU:STA HD:STA LOW 70% SCLK 30% 70% SDIO 30% START t r:IN Figure 5. 2-Wire Control Interface Read and Write Timing Parameters SCLK A6-A0, SDIO R/W START ADDRESS + R/W Figure 6. 2-Wire Control Interface Read and ...
Page 12
Si4702/03-C19 Table 8. FM Receiver Characteristics ( 2 1 Parameter Input Frequency 3,4,5,6,7 Sensitivity Sensitivity (50 matching 3,4,5,6,8 network) 8 RDS Sensitivity 8,9 LNA ...
Page 13
Table 8. FM Receiver Characteristics ( 2 1 Parameter 3,8,12 Mono/Stereo Switching Level 3,4,5,6,9 Audio Mono S/N 3,5,6,8 Audio Stereo S/N 3,4,9,12 Audio THD 13 ...
Page 14
Si4702/03-C19 2. Typical Application Schematic 1 2 FMIP 3 RFGND 4 5 RST SEN SCLK SDIO RCLK VIO 1.5 to 3.6 V Notes: 1. Place C1 close to V pin All grounds connect directly to GND plane on ...
Page 15
... RDS enables data such as station identification and song name to be displayed to the user. The Si4703-C offers a detailed RDS view and a standard view, allowing adopters to selectively choose granularity of RDS status, data, and block errors. Si4703-C software ...
Page 16
... RST is low. General purpose input/output functionality is available regardless of the state of the V supplies, or the ENABLE and DISABLE bits. 4.4. RDS/RBDS Processor and Functionality The Si4703 implements an RDS/RBDS* processor for symbol decoding, block synchronization, detection, and error correction. RDS functionality is enabled by setting the RDS bit ...
Page 17
The signal level range over which the stereo to mono blending occurs ...
Page 18
Si4702/03-C19 For additional recommendations on optimizing the seek function, consult "AN284: Si4700/01/02/03 Adjustability and Settings." 4.7. Reference Clock The Si4702/03-C19 accepts a 32.768 kHz reference clock to the RCLK pin. The reference clock is required whenever the ENABLE bit is ...
Page 19
The internal address counter then automatically wraps around to the upper ...
Page 20
... ENABLE = 0 and DISABLE = 0. Setting ENABLE = 1 and DISABLE = 0 puts the device in powerup mode. To power down the device, disable RDS to prevent any unpredictable behavior (Si4703 only), then write ENABLE and DISABLE bits to 1. After being written to 1, both bits will be cleared as part of the internal device powerdown sequence ...
Page 21
To power up the device (after power down): 1. Note that V is still supplied in this scenario supplied, refer to device initialization procedure above. 2. (Optional) Set the AHIZEN bit low to disable the dc bias ...
Page 22
Si4702/03-C19 22 Rev. 1.1 ...
Page 23
... D15 D14 D13 D12 D11 Name REV[5:0] Type R Si4702C19 Reset value = 0x1053 if ENABLE = 1 Si4702C19 Reset value = 0x1000 if ENABLE = 0 Si4703C19 Reset value = 0x1253 if ENABLE = 1 Si4703C19 Reset value = 0x1200 if ENABLE = 0 Bit Name 15:10 REV[5:0] Chip Version. 0x04 = Rev C 9:6 DEV[3:0] Device. 0 before powerup = Si4702. ...
Page 24
Si4702/03-C19 Register 02h. Power Configuration Bit D15 D14 D13 D12 D11 Name DSMUTE DMUTE MONO 0 Type R/W R/W R/W R/W Reset value = 0x0000 Bit Name 15 DSMUTE Softmute Disable Softmute enable (default Softmute disable. ...
Page 25
Bit Name 7 Reserved Reserved. Always write DISABLE Powerup Disable. Refer to “4.9. Reset, Powerup, and Powerdown”. Default = 0. 5:1 Reserved Reserved. Always write ENABLE Powerup Enable. Refer to “4.9. Reset, Powerup, and ...
Page 26
Si4702/03-C19 Register 04h. System Configuration 1 Bit D15 D14 D13 D12 Name RDSIEN STCIEN 0 RDS Type R/W R/W R/W R/W Reset value = 0x0000 Bit Name 15 RDSIEN RDS Interrupt Enable Disable Interrupt (default Enable ...
Page 27
Bit Name 3:2 GPIO2[1:0] General Purpose I High impedance (default STC/RDS interrupt. A logic high will be output unless an interrupt occurs as described below Low High. Setting STCIEN = 1 ...
Page 28
Si4702/03-C19 Register 05h. System Configuration 2 Bit D15 D14 D13 D12 D11 Name SEEKTH[7:0] Type R/W Reset value = 0x0000 Bit Name 15:8 SEEKTH[7:0] RSSI Seek Threshold. 0x00 = min RSSI (default). 0x7F = max RSSI. SEEKTH presents the logarithmic ...
Page 29
Register 06h. System Configuration 3 Bit D15 D14 D13 D12 Name SMUTER[1:0] SMUTEA[1:0] Type R/W R/W Reset value = 0x0000 Bit Name 15:14 SMUTER[1:0] Softmute Attack/Recover Rate fastest (default fast slow slowest. ...
Page 30
Si4702/03-C19 Register 07h. Test 1 Bit D15 D14 D13 Name XOSCEN AHIZEN Type R/W R/W Reset value = 0x0100 Bit Name 15 XOSCEN Crystal Oscillator Enable Disable (default Enable. The internal crystal oscillator requires an external ...
Page 31
Register 08h. Test 2 Bit D15 D14 D13 D12 Name Type Reset value = 0x0000 Bit Name 15:0 Reserved Reserved. If written, these bits should be read first and then written with their pre-existing val- ues. Do not write during ...
Page 32
Si4702/03-C19 Register 0Ah. Status RSSI Bit D15 D14 D13 D12 Name RDSR STC SF/BL AFCRL RDSS BLERA[1:0] Type Reset value = 0x0000 Bit Name 15 RDSR RDS Ready RDS group ready (default). 1 ...
Page 33
Bit Name 8 ST Stereo Indicator Mono Stereo. Stereo indication is also available on GPIO3 by setting GPIO3 04h[5:4] = 01. 7:0 RSSI[7:0] RSSI (Received Signal Strength Indicator). RSSI is measured units of dBµ ...
Page 34
Si4702/03-C19 Register 0Bh. Read Channel Bit D15 D14 D13 D12 D11 Name BLERB[1:0] BLERC[1:0] BLERD[1:0] Type R R Reset value = 0x0000 Bit Name 15:14 BLERB[1:0] RDS Block B Errors errors requiring correction 1–2 errors ...
Page 35
Register 0Ch. RDSA Bit D15 D14 D13 D12 Name Type Reset value = 0x0000 Bit Name 15:0 RDSA RDS Block A Data. Register 0Dh. RDSB Bit D15 D14 D13 D12 Name Type Reset value = 0x0000 Bit Name 15:0 RDSB ...
Page 36
Si4702/03-C19 Register 0Eh. RDSC Bit D15 D14 D13 D12 Name Type Reset value = 0x0000 Bit Name 15:0 RDSC RDS Block C Data. Register 0Fh. RDSD Bit D15 D14 D13 D12 Name Type Reset value = 0x0000 Bit Name 15:0 ...
Page 37
Pin Descriptions: Si4702/03-C19 FMIP RFGND GND RST Pin Number(s) Name FMIP 3 RFGND 4, 12, 15, PAD GND 5 RST 6 SEN 7 SCLK 8 SDIO 9 RCLK ...
Page 38
... Ordering Guide Part Description Number* Si4702-C19-GM Portable Broadcast Radio Tuner FM Stereo Si4703-C19-GM Portable Broadcast Radio Tuner FM Stereo with RDS *Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel. 38 Package Type QFN ...
Page 39
... R = Die Revision TTT = Internal Code Line 3 Marking: Circle = 0.5 mm Diameter (Bottom-Left Justified Year WW = Workweek Figure 10. Si4702 Top Mark Figure 11. Si4703 Top Mark 02 = Si4702 03 = Si4703 19 = Firmware Revision Revision C Die Internal tracking code. Pin 1 Identifier Assigned by the Assembly House. Corresponds to the last sig- nificant digit of the year and workweek of the mold date ...
Page 40
Si4702/03-C19 10. Package Outline: Si4702/03-C19 Figure 12 illustrates the package details for the Si4702/03-C19. Table 10 lists the values for the dimensions shown in the illustration. Figure 12. 20-Pin Quad Flat No-Lead (QFN) Symbol Millimeters Min Nom A 0.50 0.55 ...
Page 41
PCB Land Pattern: Si4702/03-C19 Figure 13 illustrates the PCB land pattern details for the Si4702/03-C19. Table 11 lists the values for the dimensions shown in the illustration. Figure 13. PCB Land Pattern Rev. 1.1 Si4702/03-C19 41 ...
Page 42
Si4702/03-C19 Table 11. PCB Land Pattern Dimensions Symbol Millimeters Min 2.10 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ...
Page 43
A R DDITIONAL EFERENCE AN230: Si4700/01/02/03 Programming Guide AN231: Si4700/01/02/03 Headphone and Antenna Interface Si4700/01/02/03 EVB User’s Guide AN234: Si4700/01/02/03 EVB Test Procedure AN235: Si4700/01/02/03 EVB Quick Start Guide AN243: Using RDS/RBDS with the ...
Page 44
Si4702/03-C19 OCUMENT HANGE IST Revision 0.8 to Revision 0.9 Updated Figure 1, “Reset Timing Parameters for Busmode Select Method 1 (GPIO3 = 0),” on page 6. Updated Table 3, “DC Characteristics Updated Table 7, ...
Page 45
N : OTES Si4702/03-C19 Rev. 1.1 45 ...
Page 46
... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brand names mentioned herein are trademarks or registered trademarks of their respective holder 46 Rev ...