MCF5216CVF66 Freescale Semiconductor, MCF5216CVF66 Datasheet - Page 566

• Manufacturer Part Number: MCF5216CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5216CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Operating Temperature Range: -40°C To +85°C
• No. Of Pins: 256
• Rohs Compliant: No
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Queued Analog-to-Digital Converter (QADC)
28.6.8.3 Left-Justified Unsigned Result Register (LJURR)
28.7
This subsection provides a functional description of the QADC.
28.7.1
The QADC supports byte and half-word reads and writes across a 16-bit data bus interface. All conversion
results are stored in half-word registers, and the QADC does not allow more than one result register to be
read at a time. For this reason, the QADC does not guarantee read coherency.
28-28
Bit(s)
Bit(s)
14–6
15–6
5–0
Address
5–0
15
Reset
Reset
R/W:
Field
R/W:
Field
Functional Description
Result Coherency
RESULT
RESULT
15
Name
Name
7
—
—
S
RESULT
Figure 28-17. Left-Justified Unsigned Result Register (LJURR)
R/W
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
6
The left justified, signed format corresponds to a half-scale, offset binary, two’s
complement data format. Conversion values corresponding to 1/2 full scale, 0x0200,
or higher are interpreted as positive values and have a sign bit of 0. An unsigned, right
justified conversion of 0x0200 would be represented as 0x0000 in this signed register,
where the sign = 0 and the result = 0. For an unsigned, right justified conversion of
0x3FF (full range or V
= 0 and result = 0x1FF. For an unsigned, right justified conversion of 0x0000 (V
signed equivalent in this register would be 0x8000, sign = 1 and result = 0x000, a two’s
complement value representing –512.
The conversion result is signed, left-justified data.
Reserved, should be cleared.
The conversion result is unsigned, left-justified data.
Reserved, should be cleared.
Table 28-20. LJURR Field Descriptions
Table 28-19. LJSRR Field Descriptions
5
IPSBAR + 0x19_0380, 0x19_03fe
RH
), the signed equivalent in this register would be 0x7FC0, sign
Undefined
Undefined
RESULT
R/W
Description
Description
—
R
Freescale Semiconductor
8
0
RL
), the