C8051F530-IT Silicon Laboratories Inc, C8051F530-IT Datasheet - Page 76

• Manufacturer Part Number: C8051F530-IT
• Description: IC 8051 MCU 8K FLASH 20TSSOP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F53xr

Specifications of C8051F530-IT

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.25 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 336-1343

C8051F52x/F52xA/F53x/F53xA
7. Comparator
C8051F52x/F52xA/F53x/F53xA devices include one on-chip programmable voltage comparator. The
Comparator is shown in Figure 7.1.
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0), or an asyn-
chronous “raw” output (CP0A). The asynchronous CP0A signal is available even when the system clock is
not active. This allows the Comparator to operate and generate an output with the device in STOP or SUS-
PEND mode. When assigned to a Port pin, the Comparator output may be configured as open drain or
push-pull (see Section “13.2. Port I/O Initialization” on page 125). The Comparator may also be used as a
reset source (see Section “11.5. Comparator Reset” on page 109).
The Comparator inputs are selected in the CPT0MX register (SFR Definition 7.2). The CMX0P3–CMX0P0
bits select the Comparator0 positive input; the CMX0N3–CMX0N0 bits select the Comparator0 negative
input.
Important Note About Comparator Inputs: The Port pins selected as Comparator inputs should be con-
figured as analog inputs in their associated Port configuration register and configured to be skipped by the
Crossbar (for details on Port configuration, see Section “13.3. General Purpose Port I/O” on page 127).
The Comparator output can be polled in software, used as an interrupt source, internal oscillator suspend
awakening source and/or routed to a Port pin. When routed to a Port pin, the Comparator output is avail-
able asynchronous or synchronous to the system clock; the asynchronous output is available even in
STOP or SUSPEND mode (with no system clock active). When disabled, the Comparator output (if
assigned to a Port I/O pin via the Crossbar) defaults to the logic low state, and its supply current falls to
76
P0.7*
P1.1*
P1.3*
P1.5*
P1.7*
P0.1
P0.3
P0.5
CMX0N3
CMX0N2
CMX0N1
CMX0N0
CMX0P3
CMX0P2
CMX0P1
CMX0P0
Figure 7.1. Comparator Functional Block Diagram
P0.6*
P1.0*
P1.2*
P1.4*
P1.6*
P0.0
P0.2
P0.4
'F53x/'F53xA
*Available in
CP0HYN1
CP0HYN0
CP0HYP1
CP0HYP0
CP0OUT
parts
CP0RIF
CP0EN
CP0FIF
CP0 +
CP0 -
Rev. 1.3
+
-
VDD
GND
Decision
Reset
Tree
CPT0MD
(SYNCHRONIZER)
D
SET
CLR
Q
Q
D
SET
CLR
Q
Q
Rising-edge
CP0
Crossbar
Interrupt
Logic
Falling-edge
Interrupt
CP0
CP0A
CP0
CP0