MCHC11F1CFNE3 Freescale Semiconductor, MCHC11F1CFNE3 Datasheet - Page 104

• Manufacturer Part Number: MCHC11F1CFNE3
• Description: IC MCU 8BIT 1K RAM 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MCHC11F1CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 30
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• A/d Inputs: 8-Channel, 8-Bit
• Eeprom Memory: 512 Bytes
• Input Output: 30
• Interface: SCI/SPI
• Memory Type: EPROM
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 0 Bytes
• Timers: 3-16-bit
• Voltage, Range: 3-5.5 V
• Controller Family/series: 68HC11
• No. Of I/o's: 30
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC11F
• Core: HC11
• Data Bus Width: 8 bit
• Program Memory Size: 512 B
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: RoHS Compliant part

SPIE — Serial Peripheral Interrupt Enable
SPE — Serial Peripheral System Enable
DWOM — Port D Wired-OR Mode
MSTR — Master Mode Select
CPOL — Clock Polarity
CPHA — Clock Phase
SPR[1:0] — SPI Clock Rate Selects
8-6
Set the SPE bit to one to request a hardware interrupt sequence each time the SPIF
or MODF status flag is set. SPI interrupts are inhibited if this bit is clear or if the I bit in
the condition code register is one.
When the SPE bit is set, the port D bit 2, 3, 4, and 5 pins are dedicated to the SPI func-
tion. If the SPI is in the master mode and DDRD bit 5 is set, then the port D bit 5 pin
becomes a general-purpose output instead of the SS input.
DWOM affects all port D pins.
When the clock polarity bit is cleared and data is not being transferred, the SCK pin of
the master device has a steady state low value. When CPOL is set, SCK idles high.
Refer to Figure 8-2 and 8.2.1 Clock Phase and Polarity Controls.
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relation-
ship between master and slave. The CPHA bit selects one of two different clocking
protocols. Refer to Figure 8-2 and 8.2.1 Clock Phase and Polarity Controls.
These two bits select the SPI clock (SCK) rate when the device is configured as mas-
ter. When the device is configured as slave, these bits have no effect. Refer to Table
8-1.
0 = SPI system interrupts disabled
1 = SPI system interrupts enabled
0 = SPI system disabled
1 = SPI system enabled
0 = Normal CMOS outputs
1 = Open-drain outputs
0 = Slave mode
1 = Master mode
SPR[1:0]
0 0
0 1
1 0
1 1
Divide By
E Clock
16
32
2
4
Freescale Semiconductor, Inc.
For More Information On This Product,
Frequency at
SERIAL PERIPHERAL INTERFACE
E = 2 MHz
62.5 kHz
1.0 MHz
500 kHz
125 kHz
Table 8-1 SPI Clock Rates
Go to: www.freescale.com
Frequency at
E = 3 MHz
187.5 kHz
93.7 kHz
1.5 MHz
750 kHz
Frequency at
E = 4 MHz
2.0 MHz
1.0 MHz
250 kHz
125 kHz
Frequency at
TECHNICAL DATA
156.25 kHz
78.125 kHz
E = 5 MHz
2.5 MHz
625 kHz
MC68HC11F1