P89C662HBA/00,512 NXP Semiconductors, P89C662HBA/00,512 Datasheet - Page 17

• Manufacturer Part Number: P89C662HBA/00,512
• Description: IC 80C51 MCU FLASH 32K 44-PLCC
• Manufacturer: NXP Semiconductors
• Series: 89Cr

Specifications of P89C662HBA/00,512

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 568-1269-5; 935267444512; P89C662HBA

Philips Semiconductors
In the following text, it is assumed that ENS1 = “1”.
The “START” Flag, STA: STA = “1”: When the STA bit is set to
enter a Master mode, the SIO1 hardware checks the status of the
I2C bus and generates a START condition if the bus is free. If the
bus is not free, then SIO1 waits for a STOP condition (which will free
the bus) and generates a START condition after a delay of half a
clock period of the internal serial clock generator.
If STA is set while SIO1 is already in a Master mode and one or
more bytes are transmitted or received, SIO1 transmits a repeated
START condition. STA may be set at any time. STA may also be set
when SIO1 is an addressed slave.
2002 Oct 28
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM
SHIFT ACK & S1DAT
(1) Valid data in S1DAT
(2) Shifting data in S1DAT and ACK
(3) High level on SDA
SHIFT BSD7
S1DAT
BSD7
SDA
SCL
SDA
ACK
SCL
LOADED BY THE CPU
(1)
D7
D7
(2)
(2)
D6
D6
SHIFT PULSES
(2)
(2)
Figure 6. Serial Input/Output Configuration
Figure 7. Shift-in and Shift-out Timing
D5
D5
BSD7
(2)
(2)
D4
D4
(2)
(2)
INTERNAL BUS
17
D3
D3
STA = “0”: When the STA bit is reset, no START condition or
repeated START condition will be generated.
The STOP Flag, STO: STO = “1”: When the STO bit is set while
SIO1 is in a Master mode, a STOP condition is transmitted to the
I
hardware clears the STO flag. In a Slave mode, the STO flag may
be set to recover from an error condition. In this case, no STOP
condition is transmitted to the I
behaves as if a STOP condition has been received and switches to
the defined “not addressed” Slave Receiver mode. The STO flag is
automatically cleared by hardware.
2
S1DAT
(2)
(2)
C bus. When the STOP condition is detected on the bus, the SIO1
8
D2
D2
(2)
(2)
P89C660/P89C662/P89C664/
D1
D1
(2)
(2)
ACK
D0
D0
(2)
(2)
2
C bus. However, the SIO1 hardware
(3)
A
SU00969
(1)
A
P89C668
SHIFT IN
SU00970
SHIFT OUT
Product data