ATTINY167-15MD Atmel, ATTINY167-15MD Datasheet - Page 173

• Manufacturer Part Number: ATTINY167-15MD
• Description: MCU AVR 16K FLASH 15MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY167-15MD

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Processor Series: ATTINY1x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.5.6.3
15.5.7
15.5.7.1
7728G–AVR–06/10
Data Length
Handling LBT[5..0]
Data Length in LIN 2.1
The re-synchronization implemented in the controller tolerates a clock deviation of ± 20% and
adjusts the baud rate in a ± 2% range.
The new LBT[5..0] value will be used up to the end of the response. Then, the LBT[5..0] will be
reset to 32 for the next header.
The LINBTR register can be used to (software) re-calibrate the clock oscillator.
The re-synchronization is not performed if the LIN node is enabled as a master.
LDISR bit of LINBTR register is used to:
Note that the LENA bit of LINCR register is important for this handling (see
page
Figure 15-8. Handling LBT[5..0]
Section 15.4.6 “LIN Commands” on page 167
set the LRXDL[3..0] or LTXDL[3..0] fields of LINDLR register before receiving or transmitting a
response.
In the case of Tx Response the LRXDL[3..0] will be used by the hardware to count the number
of bytes already successfully sent.
In the case of Rx Response the LTXDL[3..0] will be used by the hardware to count the number
of bytes already successfully received.
If an error occurs, this information is useful to the programmer to recover the LIN messages.
• Disable the re-synchronization (for instance in the case of LIN MASTER node),
• To enable the setting of LBT[5..0] (to manually adjust the baud rate especially in the case of
• If LTXDL[3..0]=0 only the CHECKSUM will be sent,
• If LRXDL[3..0]=0 the first byte received will be interpreted as the CHECKSUM,
• If LTXDL[3..0] or LRXDL[3..0] >8, values will be forced to 8 after the command setting and
UART mode). A minimum of 8 is required for LBT[5..0] due to the sampling operation.
before sending or receiving of the first byte.
173).
=1
Write in LINBTR register
(LINCR bit 4)
LENA ?
Enable re-synch. in LIN mode
LBT[5..0] forced to 0x20
LDISR forced to 0
=0
LDISR
to write
=0
describes how to set or how are automatically
=1
Disable re-synch. in LIN mode
LBT[5..0] = LBT[5..0] to write
ATtiny87/ATtiny167
LDISR forced to 1
(LBT[5..0]
min
=8)
Figure 15-8 on
173