ATTINY2313-20PJ Atmel, ATTINY2313-20PJ Datasheet - Page 143

• Manufacturer Part Number: ATTINY2313-20PJ
• Description: IC MCU AVR 2K FLASH 20DIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY2313-20PJ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Other names: ATTINY2313-24PJ; ATTINY2313-24PJ

2543L–AVR–08/10
Figure 64. Two-wire Mode, Typical Timing Diagram
Referring to the timing diagram (Figure 64.), a bus transfer involves the following steps:
1. The a start condition is generated by the Master by forcing the SDA low line while the
2. In addition, the start detector will hold the SCL line low after the Master has forced an
3. The Master set the first bit to be transferred and releases the SCL line (C). The Slave
4. After eight bits are transferred containing slave address and data direction (read or
5. If the Slave is addressed it holds the SDA line low during the acknowledgment cycle
6. Multiple bytes can now be transmitted, all in same direction, until a stop condition is given
If the Slave is not able to receive more data it does not acknowledge the data byte it has last
received. When the Master does a read operation it must terminate the operation by force the
acknowledge bit low after the last byte transmitted.
Figure 65. Start Condition Detector, Logic Diagram
SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of the Shift
Register, or by setting the corresponding bit in the PORT Register to zero. Note that the
Data Direction Register bit must be set to one for the output to be enabled. The slave
device’s start detector logic (Figure 65.) detects the start condition and sets the USISIF
flag. The flag can generate an interrupt if necessary.
negative edge on this line (B). This allows the Slave to wake up from sleep or complete
its other tasks before setting up the Shift Register to receive the address. This is done by
clearing the start condition flag and reset the counter.
samples the data and shift it into the serial register at the positive edge of the SCL clock.
write), the Slave counter overflows and the SCL line is forced low (D). If the slave is not
the one the Master has addressed, it releases the SCL line and waits for a new start
condition.
before holding the SCL line low again (i.e., the Counter Register must be set to 14 before
releasing SCL at (D)). Depending of the R/W bit the Master or Slave enables its output. If
the bit is set, a master read operation is in progress (i.e., the slave drives the SDA line)
The slave can hold the SCL line low after the acknowledge (E).
by the Master (F). Or a new start condition is given.
SDA
SCL
Write( USISIF)
A B
S
C
ADDRESS
SDA
SCL
1 - 7
R/W
8
D
ACK
9
E
DATA
1 - 8
D Q
CLR
ACK
9
D Q
CLR
DATA
1 - 8
USISIF
CLOCK
HOLD
ACK
9
P
F
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