ATMEGA162-16AI Atmel, ATMEGA162-16AI Datasheet - Page 118

IC MCU AVR 16K 5V 16MHZ 44-TQFP

ATMEGA162-16AI

Manufacturer Part Number
ATMEGA162-16AI
Description
IC MCU AVR 16K 5V 16MHZ 44-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA162-16AI

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA162-16AI
Manufacturer:
MIT
Quantity:
170
Part Number:
ATMEGA162-16AI
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATMEGA162-16AI
Manufacturer:
ATMEL
Quantity:
1 000
Part Number:
ATMEGA162-16AI
Manufacturer:
ATMEL
Quantity:
20 000
Compare Output Mode
and Waveform
Generation
Modes of
Operation
Normal Mode
Clear Timer on
Compare Match (CTC)
Mode
118
ATmega162/V
The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes.
For all modes, setting the COMnx1:0 = 0 tells the Waveform Generator that no action on the
OCnx Register is to be performed on the next Compare Match. For Compare Output actions in
the non-PWM modes refer to
page
page
A change of the COMnx1:0 bits state will have effect at the first Compare Match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOCnx strobe bits.
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is
defined by the combination of the Waveform Generation mode (WGMn3:0) and Compare Output
mode (COMnx1:0) bits. The Compare Output mode bits do not affect the counting sequence,
while the Waveform Generation mode bits do. The COMnx1:0 bits control whether the PWM out-
put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes
the COMnx1:0 bits control whether the output should be set, cleared or toggle at a Compare
Match
For detailed timing information refer to
The simplest mode of operation is the Normal mode (WGMn3:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the
BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOVn) will be set in
the same timer clock cycle as the TCNTn becomes zero. The TOVn Flag in this case behaves
like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow
interrupt that automatically clears the TOVn Flag, the timer resolution can be increased by soft-
ware. There are no special cases to consider in the normal mode, a new counter value can be
written anytime.
The Input Capture unit is easy to use in Normal mode. However, observe that the maximum
interval between the external events must not exceed the resolution of the counter. If the interval
between events are too long, the timer overflow interrupt or the prescaler must be used to
extend the resolution for the capture unit.
The Output Compare units can be used to generate interrupts at some given time. Using the
Output Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
In Clear Timer on Compare or CTC mode (WGMn3:0 = 4 or 12), the OCRnA or ICRn Register
are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when
the counter value (TCNTn) matches either the OCRnA (WGMn3:0 = 4) or the ICRn (WGMn3:0 =
12). The OCRnA or ICRn define the top value for the counter, hence also its resolution. This
mode allows greater control of the Compare Match output frequency. It also simplifies the oper-
ation of counting external events.
The timing diagram for the CTC mode is shown in
increases until a Compare Match occurs with either OCRnA or ICRn, and then counter (TCNTn)
is cleared.
129.
129, and for phase correct and phase and frequency correct PWM refer to
(See “Compare Match Output Unit” on page
Table 53 on page
“Timer/Counter Timing Diagrams” on page
128. For fast PWM mode refer to
117.)
Figure
51. The counter value (TCNTn)
126.
2513K–AVR–07/09
Table 55 on
Table 54 on

Related parts for ATMEGA162-16AI