SAF-TC1167-128F133HL AD Infineon Technologies, SAF-TC1167-128F133HL AD Datasheet - Page 121

• Manufacturer Part Number: SAF-TC1167-128F133HL AD
• Description: IC MCU 32BIT FLASH 176-LQFP
• Manufacturer: Infineon Technologies
• Series: TC116xr

Specifications of SAF-TC1167-128F133HL AD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 88
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 32x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFQFP
• Data Bus Width: 32 bit
• Data Ram Size: 104 KB
• Interface Type: ASC, MLI, MSC, SSC
• Maximum Clock Frequency: 133 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (12 bit, 16 Channel) / 10 bit, 4 Channel
• Packages: PG-LQFP-176
• Max Clock Frequency: 133.0 MHz
• Sram (incl. Cache): 128.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 1.0 MB
• For Use With: B158-H8690-X-0-7600IN - KIT STARTER TC116X SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SP000602800

5.3.8.3
Table 24
Parameter
Master Mode Timing
SCLK clock period
MTSR/SLSOx delay from
SCLK rising edge
MRST setup to SCLK
falling edge
MRST hold from SCLK
falling edge
Slave Mode Timing
SCLK clock period
SCLK duty cycle
MTSR setup to SCLK
latching edge
MTSR hold from SCLK
latching edge
SLSI setup to first SCLK
latching edge
SLSI hold from last SCLK
latching edge
MRST delay from SCLK
shift edge
SLSI to valid data on MRST
1) SCLK signal rise/fall times are the same as the A2 Pads rise/fall times.
2) SCLK signal high and low times can be minimum 1 ×
3)
4) Fractional divider switched off, SSC internal baud rate generation used.
Data Sheet
T
SSCmin
=
T
SYS
SSC Master / Slave Mode Timing
SSC Master/Slave Mode Timing
(Operating Conditions apply), C
= 1/
f
SYS
. When
f
SYS
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
= 80 MHz,
50
51
52
53
54
55
56
57
58
59
60
61
/
t
54
CC 2 ×
CC 0
SR 13
SR 0
SR 4 ×
SR
SR
SR
SR 7
CC 0
CC –
SR 45
t
50
= 25 ns.
Min.
T
T
T
116
SSC
SSC
SSC
T
T
T
SSC
SSC
SSC
+ 5
+ 5
+ 5
L
= 50 pF
.
Values
Typ. Max.
–
–
–
–
–
–
–
–
–
–
–
–
–
8
–
–
–
55
–
–
–
–
15
10
Electrical Parameters
Unit Note /
ns
ns
ns
ns
ns
%
ns
ns
ns
ns
ns
ns
V1.3, 2009-10
Test Con
dition
1)2)3)
–
3)
3)
1)3)
–
3)4)
3)4)
3)
–
–
–
TC1167