SAF-TC1167-128F133HL AD Infineon Technologies, SAF-TC1167-128F133HL AD Datasheet
SAF-TC1167-128F133HL AD
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SAF-TC1167-128F133HL AD Summary of contents
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TC1167 32-Bit Single-Chip Microcontroller Data Sheet V1.3 2009- ...
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... Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life ...
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TC1167 32-Bit Single-Chip Microcontroller Data Sheet V1.3 2009- ...
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... The method used for the specified thermal resistance values is included. Trademarks TriCore® trademark of Infineon Technologies AG. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. ...
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Table of Contents 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Functionality of GPTA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 ...
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Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Summary of Features • High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline – Superior real-time performance – Strong bit handling – Fully integrated DSP capabilities – Single precision Floating Point Unit (FPU) – 133 MHz operation at full ...
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ADC1) – Analog supply voltage range from 3 (single supply) – Performance for 12 bit resolution (@f • 4 different FADC input channels • Extreme fast conversion, 21 cycles of – ...
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... For the available ordering codes for the TC1167 please refer to the “Product Catalog Microcontrollers”, which summarizes all available microcontroller variants. This document describes the derivatives of the device.The derivatives and summarizes the differences. Table 1 TC1167 Derivative Synopsis Derivative SAF-TC1167-128F133HL Data Sheet Summary of Features Table 1 Ambient Temperature Range o o ...
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Introduction This Data Sheet describes the Infineon TC1167, a 32-bit microcontroller DSP, based on the Infineon TriCore Architecture. 2.1 About this Document This document is designed to be read primarily by design engineers and software engineers who need a ...
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In chapters describing the kernels ...
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Reserved, Undefined, and Unimplemented Terminology In tables where register bit fields are defined, the following conventions are used to indicate undefined and unimplemented function. Furthermore, types of bits and bit fields are defined using the abbreviations as shown in ...
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Table 3 Access Terms Symbol Description U Access Mode: Access permitted in User Mode Reset Value: Value or bit is not changed by a reset operation. SV Access permitted in Supervisor Mode. R Read-only register. 32 Only ...
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CSA Context Save Area CSFR Core Special Function Register DAP Device Access Port DAS Device Access Server DCACHE Data Cache DFLASH Data Flash Memory DGPR Data General Purpose Register DMA Direct Memory Access DMI Data Memory Interface ERU External Request ...
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NC Non Connect NMI Non-Maskable Interrupt OCDS On-Chip Debug Support OVRAM Overlay Memory PCP Peripheral Control Processor PMU Program Memory Unit PLL Phase Locked Loop PFLASH Program Flash Memory PMI Program Memory Interface PMU Program Memory Unit PRAM PCP Parameter ...
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System Architecture of the TC1167 The TC1167 combines three powerful technologies within one silicon die, achieving new levels of power, speed, and economy for embedded applications: • Reduced Instruction Set Computing (RISC) processor architecture • Digital Signal Processing (DSP) ...
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TC1167 Block Diagram Figure 1 shows the block diagram of the TC1167 SPRAM 8 KB ICACHE ( Configurable ) Loc ory ...
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System Features of the TC1167 The TC1167 has the following features: Packages • PG-LQFP-176-5 package, 0.5 mm pitch Clock Frequencies • Maximum CPU clock frequency: 133 MHz • Maximum PCP clock frequency: 133 MHz • Maximum SPB clock frequency: ...
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On Chip CPU Core The TC1167 includes a high Performance CPUand a Peripheral Control Processor. . 2.2.3.1 High-performance 32-bit CPU This chapter gives an overview about the TriCore 1 architecture. TriCore (TC1.3.1) Architectural Highlights • Unified RISC MCU/DSP • ...
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Kbyte Local Data RAM (LDRAM) – 0 Kbyte Data Cache (DACHE) • On-chip SRAMs with parity error detection 2.2.3.2 High-performance 32-bit Peripheral Control Processor The PCP is a flexible Peripheral Control Processor optimized for interrupt handling and thus ...
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Flexible interrupt-prioritizing scheme with 255 interrupt priority levels per SRN to choose from 2.3.2 Direct Memory Access Controller The TC1167 includes a fast and flexible DMA controller with independant DMA channels ( DMA Move engine). Features • independent DMA ...
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Features • Free-running 56-bit counter • All 56 bits can be read synchronously • Different 32-bit portions of the 56-bit counter can be read synchronously • Flexible interrupt generation based on compare match with partial STM content • Driven by ...
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DMA etc. STM IRQ0 Interrupt STM Control IRQ1 Enable / Disable Clock f Control STM STM_TIM5 Address Decoder PORST Figure 2 General Block Diagram of the STM Module Registers Data Sheet STM_CMP0 Compare Register 0 31 ...
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System Control Unit The following SCU introduction gives an overview about the TC1167 System Control Unit (SCU). 2.3.4.1 Clock Generation Unit The Clock Generation Unit (CGU) allows a very flexible clock generation for the TC1167. During user program execution ...
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Trigger sources that do not depend on a clock, such as the PORST. This trigger force the device into an asynchronous reset assertion independently of any clock. The activation of an asynchronous reset is asynchronous to the system clock, ...
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Program Memory Unit (PMU) The devices of the AudoF family contain at least one Program Memory Unit. This is named “PMU0”. Some devices contain additional PMUs which are named “PMU1”, … In the TC1167, the PMU0 contains the following ...
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... Tuning protection is required by the user to absolutely protect control data (e.g. for engine control), serial number and user software, stored in the Flash, from being manipulated, and to safely detect changed or disturbed data. For the internal Flash, these protection requirements are excellently fulfilled in the TC1167 with • ...
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Flash bank, whereas the Data Flash is built of two Flash banks, allowing the following combinations of concurrent Flash operations: • Read code or data from Program Flash, while one bank of Data Flash is busy with a ...
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Flash by the CPU, but may also be issued by the DMA controller (or OCDS). The Flash also features an advanced read/write protection architecture, including a read protection for the whole Flash array (optionally without Data Flash) ...
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For further operating conditions see data sheet section “Flash Memory Parameters”. Data Flash Features and Functions • 64 Kbyte on-chip Flash, configured in two independent Flash banks of equal size. • 64 bit read interface. • Erase/program one bank ...
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Data Access Overlay The data overlay functionality provides the capability to redirect data accesses by the TriCore to program memory (segments 8 memory called “overlay memory”. Depending on the device the following overlay memories can be available: • Overlay ...
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The TC1167 On-chip Debug Support (OCDS) provides a JTAG port for communication between external hardware and the system • The System Timer (STM) with high-precision, long-range timing capabilities • The TC1167 includes a power management system, a watchdog timer ...
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On-Chip Peripheral Units The TC1167 micro controller offers several versatile on-chip peripheral units such as serial controllers, timer units, and Analog-to-Digital converters. Several I/O lines on the TC1167 ports are reserved for these peripheral units to communicate with the ...
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Clock ASC Control Address Decoder EIR TBIR Interrupt TIR Control RIR To DMA Figure 5 General Block Diagram of the ASC Interface The ASC provides serial communication between the TC1167 and other microcontrollers, microprocessors, or external peripherals. The ASC ...
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Features • Full-duplex asynchronous operating modes – 8-bit or 9-bit data frames, LSB first – Parity-bit generation/checking – One or two stop bits – Baud rate from 5.0 Mbit/s to 1.19 bit MHz module clock) – Multiprocessor mode ...
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SSC Clock f Control CLC Address Decoder SSC Module (Kernel) RIR TIR Interrupt Control EIR DMA Requests Figure 6 General Block Diagram of the SSC Interface The SSC supports full-duplex and half-duplex serial synchronous communication Mbit/s ...
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Features • Master and Slave Mode operation – Full-duplex or half-duplex operation – Automatic pad control possible • Flexible data format – Programmable number of data bits bits – Programmable shift direction: LSB or MSB shift first ...
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Clock Control Address Decoder Interrupt Control To DMA ALTINL[15:0] ALTINH[15:0] EMGSTOPMSC Figure 7 General Block Diagram of the MSC Interface The downstream and upstream channels of the MSC module communicate with the external world via nine I/O lines. Eight output ...
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Command, data, and passive frame types – Start of serial frame: Software-controlled, timer-controlled, or free-running – Programmable upstream data frame length ( bits) – Transmission with or without SEL bit – Flexible chip select generation indicates status ...
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MultiCAN Controller The MultiCAN module provides two independent CAN nodes in the PG-LQFP-176-5 package, representing two serial communication interfaces. The number of available message objects is 64 Clock f Control Message Object Buffer ...
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The bit timings for the CAN nodes are derived from the module timer clock ( programmable data rate of 1 Mbit/s. External bus transceivers are connected to a CAN node via a pair of receive and transmit ...
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Static allocation commands offer compatibility with MultiCAN applications that are not list-based. • Advanced interrupt handling – interrupt output lines are available. Interrupt requests can be routed individually to one of the 16 interrupt output lines. ...
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Programmable baud rate: • Address range protection scheme to block unauthorized accesses • Multiple receiving devices supported Data Sheet (max MLI MLI SYS 40 TC1167 ...
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Figure 10 shows a general block diagram of the MLI module. f Fract. SYS Divider TR[3:0] BRKOUT Move SR[7:0] Engine Figure 10 General Block Diagram of the MLI Modules The MLI transmitter and MLI receiver communicate with other MLI receivers ...
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General Purpose Timer Array (GPTA) The TC1167 contains the General Purpose Timer Array (GPTA0). global view of the GPTA module. The GPTA provides a set of timer, compare, and capture functionalities that can be flexibly combined to form signal ...
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Functionality of GPTA0 The General Purpose Timer Array (GPTA0) provides a set of hardware modules required for high-speed digital signal processing: • Filter and Prescaler Cells (FPC) support input noise filtering and prescaler operation. • Phase Discrimination Logic units ...
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Mode, GPTA signal frequency in 3-sensor Mode • Duty Cycle Measurement (DCM) – Four independent units – 100% margin and time-out handling f – maximum resolution GPTA f – ...
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On-chip Trigger Unit • 16 on-chip trigger signals I/O Sharing Unit • Interconnecting inputs and outputs from internal clocks, FPC, GTC, LTC, ports, and MSC interface Data Sheet 45 TC1167 Introduction V1.3, 2009-10 ...
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Analog-to-Digital Converters The TC1167 includes two Analog to Digital Converter modules (ADC0, ADC1) and one Fast Analog to Digital Converter (FADC). 2.4.7.1 ADC Block Diagram The analog to digital converter module (ADC) allows the conversion of analog input values ...
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Multiplexer test mode (channel 7 input can be connected to ground via a resistor for test purposes during run time by specific control bit) • Power saving mechanisms Features of the digital part of each ADC kernel: • Independent ...
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... FADC functional blocks are: • An Input Structure containing the differential inputs and impedance control. Data Sheet f clock (262 FADC V V DDAF FAREF DDMF FAGND SSAF SSMF Data Reduction Unit A/D A/D Control Converter Stage Channel Channel Trigger Timers Control 48 ...
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... DDIF the V supply of the ADC that is sharing the FADC input pins. DDM • FADC Analog Part Power Supply (1.5 V), DDAF SSAF to be fed in externally • FADC Reference Voltage (3.3 V max.) and FADC Reference Ground FAREF FAGND Input Structure The input structure of the FADC in the TC1167 contains: • ...
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... Means to request all kinds of reset without usage of sideband pins. • Halt-after-Reset for repeatable debug sessions. Data Sheet Channel Amplifier Stages V DDMF V SSMF V DDMF V SSMF V DDMF V SSMF V DDMF V SSMF SSMF 50 TC1167 Introduction Converter Stage conversion A/D control Control gain CHNR A DDAF SSAF MCA06432_m4n V1.3, 2009-10 ...
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Different Boot modes to use application software not yet programmed to the Flash. • A total of four hardware breakpoints for the TriCore based on instruction address, data address or combination of both. • Unlimited number of software breakpoints ...
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Invalidation of the Data Cache (maintaining write-back data) can be done concurrently with the same SFR. • 256 KB additional Overlay RAM on Emulation Device. • The 256 KB Trace memory of the Emulation Device can optionally be used ...
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Pinning 3.1 TC1167 Pin Definition and Functions Figure 15 shows the Logic Symbol of the device. PORST TES TMODE General Control TRST TCK / CDS / TDI / BRKIN JTAG Control TDO ...
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TC1167 Pin Configuration: PG-LQFP-176-5 This chapter shows the pin configuration of the package variant PG-LQFP-176-5 OUT 40 /OUT 8/IN 40/IN 26/ P 5.0 1 OUT 41 /OUT 9/IN 41/IN 27/ P 5.1 2 OUT 42 /OUT 10 /IN 42/IN ...
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Table 4 Pin Definitions and Functions (PG-LQFP-176-5 Package Pin Symbol Ctrl. Port 0 145 P0.0 I/O0 IN0 I IN0 I HWCFG0 I OUT0 O1 OUT56 O2 OUT0 O3 146 P0.1 I/O0 IN1 I IN1 I HWCFG1 I OUT1 O1 OUT57 ...
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Table 4 Pin Definitions and Functions (PG-LQFP-176-5 Package Pin Symbol Ctrl. 166 P0.4 I/O0 IN4 I IN4 I HWCFG4 I OUT4 O1 OUT60 O2 OUT4 O3 167 P0.5 I/O0 IN5 I IN5 I HWCFG5 I OUT5 O1 OUT61 O2 OUT5 ...
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Table 4 Pin Definitions and Functions (PG-LQFP-176-5 Package Pin Symbol Ctrl. 149 P0.8 I/O0 IN8 I IN8 I OUT8 O1 OUT64 O2 OUT8 O3 150 P0.9 I/O0 IN9 I IN9 I OUT9 O1 OUT65 O2 OUT9 O3 151 P0.10 I/O0 ...
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Table 4 Pin Definitions and Functions (PG-LQFP-176-5 Package Pin Symbol Ctrl. 169 P0.13 I/O0 IN13 I OUT13 O1 OUT69 O2 OUT13 O3 175 P0.14 I/O0 IN14 I REQ4 I OUT14 O1 OUT70 O2 OUT14 O3 176 P0.15 I/O0 IN15 I ...
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Table 4 Pin Definitions and Functions (PG-LQFP-176-5 Package Pin Symbol Ctrl. 93 P1.2 I/O0 IN18 I OUT18 O1 OUT74 O2 OUT18 O3 98 P1.3 I/O0 IN19 I IN19 I OUT19 O1 OUT75 O2 OUT19 O3 107 P1.4 I/O0 IN20 I ...
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Table 4 Pin Definitions and Functions (PG-LQFP-176-5 Package Pin Symbol Ctrl. 110 P1.7 I/O0 IN23 I IN23 I OUT23 O1 OUT79 O2 OUT23 O3 94 P1.8 I/O0 IN24 I IN48 I MTSR1B I OUT24 O1 OUT48 O2 MTSR1B O3 95 ...
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Table 4 Pin Definitions and Functions (PG-LQFP-176-5 Package Pin Symbol Ctrl. 97 P1.11 I/O0 IN27 I IN51 I SCLK1B I OUT27 O1 OUT51 O2 SCLK1B O3 73 P1.12 I/O0 IN16 I AD0EMUX0 O1 AD0EMUX0 O2 OUT16 O3 72 P1.13 I/O0 ...
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Table 4 Pin Definitions and Functions (PG-LQFP-176-5 Package Pin Symbol Ctrl. 74 P2.0 I/O0 IN32 I OUT32 O1 TCLK0 O2 OUT28 O3 75 P2.1 I/O0 IN33 I TREADY0A I OUT33 O1 SLSO03 O2 SLSO13 O3 76 P2.2 I/O0 IN34 I ...
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Table 4 Pin Definitions and Functions (PG-LQFP-176-5 Package Pin Symbol Ctrl. 79 P2.5 I/O0 IN37 I OUT37 O1 RREADY0A O2 OUT110 O3 80 P2.6 I/O0 IN38 I RVALID0A I OUT38 O1 OUT38 O2 OUT111 O3 81 P2.7 I/O0 IN39 I ...
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Table 4 Pin Definitions and Functions (PG-LQFP-176-5 Package Pin Symbol Ctrl. 161 P2.10 I/O0 MRST1A I IN10 I MRST1A O1 OUT0 O2 Reserved O3 162 P2.11 I/O0 SCLK1A I IN11 I SCLK1A O1 OUT1 O2 FCLP0B O3 163 P2.12 I/O0 ...
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Table 4 Pin Definitions and Functions (PG-LQFP-176-5 Package Pin Symbol Ctrl. 136 P3.0 I/O0 RXD0A I RXD0A O1 RXD0A O2 OUT84 O3 135 P3.1 I/O0 TXD0 O1 TXD0 O2 OUT85 O3 129 P3.2 I/O0 SCLK0 I SCLK0 O1 SCLK0 O2 ...
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Table 4 Pin Definitions and Functions (PG-LQFP-176-5 Package Pin Symbol Ctrl. 127 P3.6 I/O0 SLSO01 O1 SLSO11 O2 SLSOANDO1 O3 131 P3.7 I/O0 SLSI01 I SLSO02 O1 SLSO12 O2 OUT89 O3 128 P3.8 I/O0 SLSO06 O1 TXD1 O2 OUT90 O3 ...
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Table 4 Pin Definitions and Functions (PG-LQFP-176-5 Package Pin Symbol Ctrl. 143 P3.12 I/O0 RXDCAN0 I RXD0B I RXD0B O1 RXD0B O2 OUT94 O3 142 P3.13 I/O0 TXDCAN0 O1 TXD0 O2 OUT95 O3 134 P3.14 I/O0 RXDCAN1 I RXD1B I ...
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Table 4 Pin Definitions and Functions (PG-LQFP-176-5 Package Pin Symbol Ctrl. 87 P4.1 I/O0 IN29 I IN53 I OUT29 O1 OUT53 O2 Reserved O3 88 P4.2 I/O0 IN30 I IN54 I OUT30 O1 OUT54 O2 EXTCLK1 O3 90 P4.3 I/O0 ...
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Table 4 Pin Definitions and Functions (PG-LQFP-176-5 Package Pin Symbol Ctrl. 2 P5.1 I/O0 IN41 I IN27 I OUT41 O1 OUT9 O2 Reserved O3 3 P5.2 I/O0 IN42 I IN28 I OUT42 O1 OUT10 O2 Reserved O3 4 P5.3 I/O0 ...
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Table 4 Pin Definitions and Functions (PG-LQFP-176-5 Package Pin Symbol Ctrl. 7 P5.6 I/O0 IN46 I IN31 I OUT46 O1 OUT14 O2 Reserved O3 8 P5.7 I/O0 IN47 I OUT47 O1 OUT15 O2 Reserved O3 13 P5.8 I/O0 RDATA0B I ...
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Table 4 Pin Definitions and Functions (PG-LQFP-176-5 Package Pin Symbol Ctrl. 17 P5.12 I/O0 TDATA0 O1 SLSO07 O2 OUT93 O3 18 P5.13 I/O0 TVALID0B O1 SLSO16 O2 Reserved O3 19 P5.14 I/O0 TREADY0B I Reserved O1 Reserved O2 OUT94 O3 ...
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Table 4 Pin Definitions and Functions (PG-LQFP-176-5 Package Pin Symbol Ctrl. 158 P6.2 I/O0 IN24 I SON0 O1 OUT82 O2 OUT6 O3 159 P6.3 I/O0 IN25 I SOP0A O1 OUT83 O2 OUT7 O3 Analog Input Port 67 AN0 I 66 ...
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... DDM SSM 52 AREF0 V - AREF1 AGND0 DDMF DDAF 25 SSMF V - SSAF FAREF FAGND Data Sheet Type Function D Analog Input 19 D Analog Input 20 D Analog Input 21 D Analog Input 22 D Analog Input 23 D Analog Input 24 D Analog Input 25 D Analog Input 26 D Analog Input 27 D ...
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Table 4 Pin Definitions and Functions (PG-LQFP-176-5 Package Pin Symbol Ctrl 68, 84, 89, 99, 123, 153, 170 V 11, - DDP 20, 69, 83, 91, 100, 124, 139, 154, 171 V 12, ...
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Table 4 Pin Definitions and Functions (PG-LQFP-176-5 Package Pin Symbol Ctrl. 111 TDI I BRKIN I BRKOUT O 112 TMS I DAP1 I/O 113 TDO I/O DAP2 I/O BRKIN I BRKOUT O 114 TRST I 115 TCK I DAP0 I ...
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O2 = Output with IOCR bit field selection PCx = 1X10 O3 = Output with IOCR bit field selection PCx = 1X11(ALT3) Column “Type” Pad class A1 (LVTTL Pad class A2 (LVTTL Pad class ...
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Identification Registers The Identification Registers uniquely identify a module or the whole device. Table 4-1 TC1167 Identification Registers Short Name Value ADC0_ID 0058 C000 ADC1_ID 0058 C000 ASC0_ID 0000 4402 ASC1_ID 0000 4402 CAN_ID 002B C061 CBS_JDPID 0000 6350 ...
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Table 4-1 TC1167 Identification Registers (cont’d) Short Name Value SCU_MANID 0000 1820 SCU_RTID 0000 0007 SSC0_ID 0000 4511 SSC1_ID 0000 4511 STM_ID 0000 C006 Data Sheet Address F000 0644 H H F000 0648 H H F010 0108 H H F010 ...
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Electrical Parameters 5.1 General Parameters 5.1.1 Parameter Interpretation The parameters listed in this section partly represent the characteristics of the TC1167 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a ...
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Pad Driver and Pad Classes Summary This section gives an overview on the different pad driver classes and its basic characteristics. More details (mainly DC parameters) are defined in the Table 6 Pad Driver and Pad Classes Overview Class ...
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... Voltage on any Class A input pin and dedicated input pins V with respect to SS Voltage on any Class D analog input pin with respect to V AGND Voltage on any Class D analog input pin with respect the FADC is SSAF switched through to the pin Applicable for , , DD DDOSC 2) Applicable for and ...
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Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the TC1167. All parameters specified in the following table refer to these operating conditions, unless otherwise noted. Table 8 Operating Condition Parameters ...
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Table 8 Operating Condition Parameters Parameter Absolute sum of short circuit currents of a pin group (see Table 9) Inactive device pin current Absolute sum of short circuit currents of the device External load capacitance 1) Digital supply voltages applied ...
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Table 9 Pin Groups for Overload/Short-Circuit Current Sum Parameter Group Pins 5 P1.[7:4]; TDI/BRKIN/BRKOUT; TRST, TCK/DAP0; P1.[1:0]; P1.15; TESTMODE; ESR0; PORST; ESR1 6 P3.[10:0]; P3.[15:14] 7 P3.[13:11]; P0.[3:0]; P0.[11:8] 8 P6.[3:0]; P2.[13:8]; P0.[5:4]; P0.[13:12] 9 P0.[7:6]; P0.[15:14]; P5.[7:0]; P5.15 Data ...
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DC Parameters 5.2.1 Input/Output Pins Table 10 Input/Output DC-Characteristics (Operating Conditions apply) Parameter Symbol General Parameters 1) Pull-up current | I | PUH I Pull-down | | PDL 1) current 1) C Pin capacitance IO (Digital I/O) Input only ...
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Table 10 Input/Output DC-Characteristics (cont’d)(Operating Conditions apply) Parameter Symbol t Spike filter pass- SF2 through pulse duration V Class A Pads ( = 3. 3.3V ± 5%) DDP V Output low voltage OLA 2)3) V Output ...
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Table 10 Input/Output DC-Characteristics (cont’d)(Operating Conditions apply) Parameter Symbol I Input leakage OZA1 current Class A1 pins Class F Pads, LVDS Mode ( V Output low voltage OL V Output high OH voltage V Output differential OD voltage V Output ...
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Maximum resistance of the driver Ω for strong driver mode, 200 / 150 Ω for medium driver mode, 600 / 400 Ω for weak driver mode, verified by design / characterization. 4) Function verified by design, ...
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Analog to Digital Converters (ADC0/ADC1) All ADC parameters are optimized for and valid in the range of Table 11 ADC Characteristics (Operating Conditions apply) Parameter Symbol Analog supply V DDM voltage Analog ground SSM voltage V ...
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Table 11 ADC Characteristics (cont’d) (Operating Conditions apply) Parameter Symbol 9)5) EA Offset error OFF I Input leakage CC OZ1 current at analog inputs of ADC0/1 11) 12) 13) Input leakage I OZ2 current AREF0/1 per module ...
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Table 11 ADC Characteristics (cont’d) (Operating Conditions apply) Parameter Symbol C Switched AINSW capacitance at the analog voltage inputs R ON resistance of AIN the transmission gates in the analog voltage path R ON resistance AIN7T for the ADC test ...
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Only one of these parameters is tested, the other is verified by design characterization. 13) The leakage current decreases typically 30% for junction temperature decrease of 10 14) Applies to AINx, when used as auxiliary reference inputs. 15) I ...
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Table 12 Conversion Time (Operating Conditions apply) Parameter Symbol CC 2 × t Conversion C time with post-calibration Conversion time without post-calibration R EXT AIN EXT V AREF Figure 18 ADC0/ADC1 Input Circuits ...
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... Note / Test Condition 9) LSB 9) LSB % Without calibration gain Without calibration gain With calibration 3) mV Without calibration mV – – – V – 4)6) V Nominal 3 – SSAF V – DDMF mA – μA Independent of rms conversion < IN μ < IN V1.3, 2009-10 TC1167 1) V < DDMF V < DDMF ...
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Table 13 FADC Characteristics (Operating Conditions apply) (cont’d) Parameter Symbol t Conversion time C_FADC Converter clock f FADC R Input resistance of FAIN the analog voltage path (Rn, Rp) Channel amplifier f COFF 9) cutoff frequency Settling time of a ...
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FAINxN V FAGND FAINxP V V FAREF V Figure 20 FADC Input Circuits Data Sheet FADC Analog Input Stage FAREF R P FADC Reference Voltage Input Circuitry FAREF I FAREF FAGND 95 Electrical Parameters - + /2 ...
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Oscillator Pins Table 14 Oscillator Pins Characteristics (Operating Conditions apply) Parameter Symbol f Frequency range OSC V Input low voltage at ILX 1) XTAL1 Input high voltage at V IHX 1) XTAL1 I Input current at IX1 XTAL1 1) ...
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The following formula calculates the temperature measured by the DTS in [ RESULT bitfield of the DTSSTAT register. Data Sheet DTSSTAT RESULT Tj = ----------------------------------------------------------------- - TC1167 Electrical Parameters o C] from the 619 – V1.3, ...
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Power Supply Current The default test conditions (differences explicitly specified) are 1. 3. DDP Table 16 Power Supply Currents, Maximum Power Consumption Parameter Symbol I Core active mode 1)2) supply current Realistic ...
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The I maximum value is 180 The dependency in this range is, at constant junction temperature, linear 1:1 mode. CPU SYS 4) Not tested in production separately, verified by design / characterization. ...
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AC Parameters All AC parameters are defined with the temperature compensation disabled. That means, keeping the pads constantly at maximum strength. 5.3.1 Testing Waveforms 90% 10 Figure 21 Rise/Fall Time Parameters V D ...
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Output Rise/Fall Times Table 17 Output Rise/Fall Times (Operating Conditions apply) Parameter Symbol Class A1 Pads Rise/fall times , RA1 FA1 Class A2 Pads t t Rise/fall times , RA2 FA2 1) Class F Pads Rise/fall ...
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Power Sequencing V 5V 3.3V 1.5V V DDP Figure 3 1.5 V Power-Up/Down Sequence The following list of rules applies to the power-up/down sequence All ground pins must be externally connected ...
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The PORST signal may be deactivated after all supplies and the oscillator have reached stable operation, within the normal operating conditions normal power down the PORST signal should be activated within the normal operating range, and then ...
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Power, Pad and Reset Timing Table 18 Power, Pad and Reset Timing Parameters Parameter Min. V voltage to DDP ensure defined pad 1) states 2) Oscillator start-up time Minimum PORST active time after power supplies are stable at operating ...
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OSCS 0,3 × This parameter is verified by device characterization. The external oscillator circuitry must be DDOSC3 optimized by the customer and checked for negative resistance as recommended and specified ...
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Phase Locked Loop (PLL) Note: All PLL characteristics defined on this and the next page are not subject to production test, but verified by design characterization. Table 19 PLL Parameters (Operating Conditions apply) Parameter Accumulated jitter VCO frequency range ...
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With rising number of clock cycles the maximum jitter increases linearly value m of that is defined by the K2-factor of the PLL. Beyond this value of accumulated jitter remains at a constant value. Further, a ...
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These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the supply pins and using PCB supply and ground planes. Data Sheet Electrical Parameters 108 TC1167 V1.3, 2009-10 ...
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JTAG Interface Timing The following parameters are applicable for communication through the JTAG debug interface. The JTAG module is fully compliant with IEEE1149.1-2000. Note: These parameters are not subject to production test but verified by design and/or characterization. Table ...
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V 0 Figure 27 Test Clock Timing (TCK) TCK TMS TDI t 9 TDO Figure 28 JTAG Timing Data Sheet 110 ...
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DAP Interface Timing The following parameters are applicable for communication through the DAP debug interface. Note: These parameters are not subject to production test but verified by design and/or characterization. Table 21 DAP Interface Timing Parameters (Operating Conditions apply) ...
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DAP0 DAP1 Figure 30 DAP Timing Host to Device DAP1 Figure 31 DAP Timing Device to Host Data Sheet Electrical Parameters 112 TC1167 MC_ DAP1_RX MC_ DAP1_TX V1.3, ...
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Peripheral Timings Note: Peripheral timing parameters are not subject to production test. They are verified by design / characterization. 5.3.8.1 Micro Link Interface (MLI) Timing MLI Transmitter Timing TCLKx TDATAx TVALIDx TREADYx MLI Receiver Timing RCLKx RDATAx RVALIDx RREADYx ...
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Table 22 MLI Transmitter/Receiver Timing (Operating Conditions apply), C Parameter MLI Transmitter Timing TCLK clock period TCLK high time TCLK low time TCLK rise time TCLK fall time TDATA/TVALID output delay time TREADY setup time to TCLK rising edge TREADY ...
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The RCLK max. input rise/fall times are best case parameters for input signal rise/fall times can be used for longer RCLK clock periods. 5.3.8.2 Micro Second Channel (MSC) Interface Timing Table 23 MSC Interface Timing (Operating Conditions apply), C ...
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SSC Master / Slave Mode Timing Table 24 SSC Master/Slave Mode Timing (Operating Conditions apply), C Parameter Master Mode Timing SCLK clock period MTSR/SLSOx delay from SCLK rising edge MRST setup to SCLK falling edge MRST hold from SCLK ...
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SCLK 1) MTSR 1) MRST 2) SLSOx 1) This timing is based on the following setup: CON.PH = CON. The transition at SLSOx is based on the following setup: SSOTC.TRAIL = 0 and the first SCLK ...
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Package and Reliability 5.4.1 Package Parameters Table 25 Thermal Parameters (Operating Conditions apply) Device Package TC1167 PG-LQFP-176-5 1) The top and bottom thermal resistances between the case and the ambient ( with the thermal resistances between the junction and ...
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Package Outline Figure 36 PG-LQFP-176-5, Plastic Green Low Profile Quad Flat Package You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Data Sheet Electrical Parameters 119 TC1167 V1.3, 2009-10 ...
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Flash Memory Parameters The data retention time of the TC1167’s Flash memory (i.e. the time after which stored data can still be retrieved) depends on the number of times the Flash memory has been erased and programmed. Table 26 ...
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Quality Declarations Table 27 Quality Parameters Parameter Symbol Operation Lifetime ESD susceptibility V HBM according to Human Body Model (HBM) V ESD susceptibility HBM1 of the LVDS pins V ESD susceptibility CDM according to Charged Device ...
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