MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 60

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

SPBR — Serial Clock Baud Rate
SPCR1 — QSPI Control Register 1
SPE — QSPI Enable
DSCKL — Delay before SCK
DTL — Length of Delay after Transfer
60
RESET:
SPE
15
0
The QSPI uses a modulus counter to derive SCK baud rate from the MCU system clock. Baud rate is
selected by writing a value from 2 to 255 into the SPBR field. The following equation determines the
SCK baud rate:
where SPBR equals {2, 3, 4,..., 255}
Giving SPBR a value of zero or one disables the baud rate generator. SCK is disabled and assumes its
inactive state value. No serial transfers occur. At reset, baud rate is initialized to one eighth of the sys-
tem clock frequency.
SPCR1 contains parameters for configuring the QSPI before it is enabled. The CPU can read and write
this register, but the QSM has read access only, except for SPE, which is automatically cleared by the
QSPI after completing all serial transfers, or when a mode fault occurs.
When the DSCK bit in command RAM is set, this field determines the length of delay from PCS valid to
SCK transition. PCS can be any of the four peripheral chip-select pins. The following equation deter-
mines the actual delay before SCK:
where DSCKL equals {1, 2, 3,..., 127}.
When the DSCK value of a queue entry equals zero, then DSCKL is not used. Instead, the PCS valid-
to-SCK transition is one-half SCK period.
When the DT bit in command RAM is set, this field determines the length of delay after serial transfer.
The following equation is used to calculate the delay:
where DTL equals {1, 2, 3,..., 255}.
A zero value for DTL causes a delay-after-transfer value of 8192/System Clock.
If DT equals zero, a standard delay is inserted.
Delay after transfer can be used to provide a peripheral deselect interval. A delay can also be inserted
between consecutive transfers to allow serial A/D converters to complete conversion.
0 = QSPI is disabled. QSPI pins can be used for general-purpose I/O.
1 = QSPI is enabled. Pins allocated by PQSPAR are controlled by the QSPI.
14
0
0
0
Freescale Semiconductor, Inc.
DSCKL
Standard Delay after Transfer = [17/System Clock]
For More Information On This Product,
0
Delay after Transfer = [(32DTL)/System Clock]
PCS to SCK Delay = [DSCKL/System Clock]
SPBR = System Clock/(2SCK)(Baud Rate Desired)
1
SCK Baud Rate = System Clock/(2SPBR)
Go to: www.freescale.com
0
8
0
or
7
0
0
0
0
DTL
0
1
MC68331TS/D
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0
0
0