MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 49
MC68331CEH25
Manufacturer Part Number
MC68331CEH25
Description
IC MCU 32BIT 25MHZ 132-PQFP
Manufacturer
Freescale Semiconductor
Series
M683xxr
Specifications of MC68331CEH25
Core Processor
CPU32
Core Size
32-Bit
Speed
25MHz
Connectivity
EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
18
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
132-QFP
Controller Family/series
68K
No. Of I/o's
18
Cpu Speed
25MHz
No. Of Timers
1
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
2
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Processor Series
M683xx
Core
CPU32
Data Bus Width
32 bit
Data Ram Size
80 B
Interface Type
QSPI, SCI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
18
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68331CEH25
Manufacturer:
PANASONIC
Quantity:
2 000
Company:
Part Number:
MC68331CEH25
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MC68331CEH25
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
MC68331TS/D
TBLSN/TBLUN
1. Privileged instruction.
TBLS/TBLU
Instruction
TRAPcc
TRAPV
SWAP
SUBQ
SUBA
SUBX
TRAP
UNLK
SUBI
SUB
TAS
TST
#<data>, <ea>
#<data>, <ea>
Dym : Dyn, Dn
Dym : Dyn, Dn
(An),
<ea>, Dn
Dn, <ea>
<ea>, An
<ea>, Dn
<ea>, Dn
#<data>
#<data>
Syntax
Dn, Dn
<ea>
none
none
<ea>
Freescale Semiconductor, Inc.
Table 20 Instruction Set Summary (Continued)
Dn
An
For More Information On This Product,
(An)
Go to: www.freescale.com
Operand Size
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
16, 32
16, 32
none
none
none
16
32
8
Destination
Destination
Destination
Destination
Destination
Destination Tested Condition Codes bit 7 of
Destination
Dyn
(Temp
(Dym
Dyn
(Temp
Dym
SSP
SSP
vector address
If cc true, then TRAP exception
If V set, then overflow TRAP exception
Source
An
SP; (SP)
Dym
Dym
2
4
Temp
256)
Dn [7 : 0])
Dn [7 : 0]) / 256
0, to set condition codes
SSP; format/vector offset
SSP; PC
Source
Source
Data
Data
Source
Temp
Temp
Temp
Dn
PC
An, SP
MSW
Operation
Destination
Destination
Temp
X
Dn
(SSP); SR
Destination
Destination
Temp
4
Destination
LSW
SP
(SSP);
(SSP);
49