Z8F0412SJ020SG Zilog, Z8F0412SJ020SG Datasheet - Page 146

• Manufacturer Part Number: Z8F0412SJ020SG
• Description: IC ENCORE MCU FLASH 4K 28SOIC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0412SJ020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: Z8F041xx
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4107; Z8F0412SJ020SG

PS022517-0508
Address Only Transaction with a 10-bit Address
14. If more bytes remain to be sent, return to
15. Software responds by setting the STOP bit of the I
16. The I
17. The slave can either Acknowledge or Not Acknowledge the last byte. Because either
18. The I
In the situation where software wants to determine if a slave with a 10-bit address is
responding without sending or receiving data, a transaction is done which only consists of
an address phase.
with 10-bit address will acknowledge. As an example, this transaction is used after a
“write” has been done to a EEPROM to determine when the EEPROM completes its inter-
nal write operation and is once again responding to I2C transactions. If the slave does not
Acknowledge the transaction is repeated until the slave is able to Acknowledge.
Follow the steps below for an address only transaction to a 10-bit addressed slave:
1. Software asserts the IEN bit in the I
2. Software asserts the TXI bit of the I
3. The I
4. Software responds to the TDRE interrupt by writing the first slave address byte. The
5. Software asserts the START bit of the I
6. The I
7. The I
8. After one bit of address is shifted out by the SDA signal, the Transmit Interrupt is
S
to initiate a new transaction). In the STOP case, software clears the TXI bit of the I
Control Register at the same time.
the STOP or START bit is already set, the NCKI interrupt does not occur.
STOP or START bit is cleared.
least-significant bit must be 0 for the write operation.
Register.
asserted.
Slave Address
Figure 28. 10-Bit Address Only Transaction Format
1st 7 bits
2
2
2
2
2
C Controller completes transmission of the data on the SDA signal.
C Controller sends the STOP (or RESTART) condition to the I
C interrupt asserts, because the I
C Controller sends the START condition to the I
C Controller loads the I
Figure 28
W = 0 A/A
displays this “address only” transaction to determine if a slave
2
C Shift register with the contents of the I
2
2
C Control Register.
C Control Register to enable Transmit interrupts.
2
2
Slave Address
C Data Register is empty (TDRE = 1)
C Control Register.
step
2nd Byte
9.
2
C Control Register (or START bit
Z8 Encore! XP
2
C Slave.
Product Specification
A/A P
®
2
C bus. The
F0822 Series
2
C Data
I2C Controller
2
C
133