ST7FLITES2Y0M6 STMicroelectronics, ST7FLITES2Y0M6 Datasheet - Page 65

• Manufacturer Part Number: ST7FLITES2Y0M6
• Description: MCU 8BIT 1K FLASH 16SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITES2Y0M6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (3.9mm Width)
• Controller Family/series: ST7
• No. Of I/o's: 13
• Ram Memory Size: 128Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SPI
• No. Of Pwm Channels: 1
• Rohs Compliant: Yes
• Processor Series: ST7FLITESx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 2
• Operating Supply Voltage: 2.4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLIT0-IND/USB, ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• For Use With: 497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: In Transition
• Other names: 497-4861

SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.5.4 Single Master Systems
A typical single master system may be configured,
using an MCU as the master and four MCUs as
slaves (see
The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
Figure 43. Single Master / Multiple Slave Configuration
5V
Figure
MOSI
SCK
SS
SCK
MOSI
MCU
Master
Slave
MCU
43).
MISO
MISO
SS
MOSI
SCK
MCU
Slave
MISO
SS
Note: To prevent a bus conflict on the MISO line
the master allows only one active slave device
during a transmission.
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written to its SPIDR
register.
Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
MOSI
SCK
MCU
Slave
MISO
SS
ST7LITE0xY0, ST7LITESxY0
MOSI
SCK
MCU
Slave
MISO
SS
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