PIC18F4620-E/PT Microchip Technology, PIC18F4620-E/PT Datasheet - Page 11

• Manufacturer Part Number: PIC18F4620-E/PT
• Description: IC MCU FLASH 32KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4620-E/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3986 B
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3DB18F4620 - BOARD DAUGHTER ICEPIC3
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

31. Module: MSSP
© 2008 Microchip Technology Inc.
In SPI mode, the Buffer Full flag (BF bit in the
SSPSTAT register), the Write Collision Detect bit
(WCOL bit in SSPCON1) and the Receive
Overflow Indicator bit (SSPOV in SSPCON1) are
not reset upon disabling the SPI module (by
clearing the SSPEN bit in the SSPCON1 register).
For example, if SSPBUF is full (BF bit is set) and
the MSSP module is disabled and re-enabled, the
BF bit will remain set. In SPI Slave mode, a sub-
sequent write to SSPBUF will result in a write
collision. Also, if a new byte is received, a receive
overflow will occur.
Work around
Ensure that if the buffer is full, SSPBUF is read
(thus clearing the BF flag) and WCOL is clear
before disabling the MSSP module. If the module
is configured in SPI Slave mode, ensure that the
SSPOV bit is clear before disabling the module.
Date Codes that pertain to this issue:
All engineering and production devices.
PIC18F2525/2620/4525/4620
32. Module: MSSP (SPI Mode)
FIGURE 1:
EXAMPLE 5:
LOOP BTFSS SSPSTAT, BF
When the SPI is using Timer2/2 as the clock
source, a shorter than expected SCK pulse may
occur on the first bit of the transmitted/received
data (Figure 1).
Work around
To avoid producing the short pulse, turn off Timer2
and clear the TMR2 register, load the SSPBUF
with the data to transmit and then turn Timer2 back
on. Refer to Example 5 for sample code.
Date Codes that pertain to this issue:
All engineering and production devices.
SDO
SCK
BRA
MOVF
MOVWF RXDATA
MOVF
BCF
CLRF
MOVWF SSPBUF
BSF
Write SSPBUF
LOOP
SSPBUF, W
TXDATA, W
T2CON, TMR2ON
TMR2
T2CON, TMR2ON
bit 0 = 1 bit 1 = 0
SCK PULSE VARIATION
USING TIMER2/2
AVOIDING THE INITIAL
SHORT SCK PULSE
;Data received?
;(Xmit complete?)
;No
;W = SSPBUF
;Save in user RAM
;W = TXDATA
;Timer2 off
;Clear Timer2
;Xmit New data
;Timer2 on
bit 2 = 1
DS80224E-page 11
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