PIC18LF14K22-I/ML Microchip Technology, PIC18LF14K22-I/ML Datasheet - Page 156

• Manufacturer Part Number: PIC18LF14K22-I/ML
• Description: IC PIC MCU FLASH 512KX16 20-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF14K22-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, MSSP, SPI, USART
• Maximum Clock Frequency: 32 KHz
• Number Of Programmable I/os: 18
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F1XK22/LF1XK22
14.3.4
Both 7-bit and 10-bit Slave modes implement
automatic clock stretching during a transmit sequence.
The SEN bit of the SSPCON2 register allows clock
stretching to be enabled during receives. Setting SEN
will cause the SCL pin to be held low at the end of
each data receive sequence.
14.3.4.1
In 7-bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence if the BF
bit is set, the CKP bit of the SSPCON1 register is
automatically cleared, forcing the SCL output to be
held low. The CKP being cleared to ‘0’ will assert the
SCL line low. The CKP bit must be set in the user’s
ISR before reception is allowed to continue. By holding
the SCL line low, the user has time to service the ISR
and read the contents of the SSPBUF before the
master device can initiate another data transfer
sequence. This will prevent buffer overruns from
occurring (see Figure 14-13).
14.3.4.2
In 10-bit Slave Receive mode during the address
sequence, clock stretching automatically takes place
but CKP is not cleared. During this time, if the UA bit is
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address and following the receive of the second
byte of the 10-bit address with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPADD. Clock stretching will occur on each data
receive sequence as described in 7-bit mode.
DS41365D-page 156
Note 1: If the user reads the contents of the
2: The CKP bit can be set by software
CLOCK STRETCHING
SSPBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
Clock Stretching for 7-bit Slave
Receive Mode (SEN =
Clock Stretching for 10-bit Slave
Receive Mode (SEN = 1)
1
)
Preliminary
14.3.4.3
7-bit Slave Transmit mode implements clock stretch-
ing by clearing the CKP bit after the falling edge of the
ninth clock. This occurs regardless of the state of the
SEN bit.
The user’s ISR must set the CKP bit before transmis-
sion is allowed to continue. By holding the SCL line
low, the user has time to service the ISR and load the
contents of the SSPBUF before the master device can
initiate
Figure 14-9).
14.3.4.4
In 10-bit Slave Transmit mode, clock stretching is con-
trolled during the first two address sequences by the
state of the UA bit, just as it is in 10-bit Slave Receive
mode. The first two addresses are followed by a third
address sequence which contains the high-order bits
of the 10-bit address and the R/W bit set to ‘1’. After
the third address sequence is performed, the UA bit is
not set, the module is now configured in Transmit
mode and clock stretching is automatic with the hard-
ware clearing CKP, as in 7-bit Slave Transmit mode
(see Figure 14-11).
Note 1: If the user loads the contents of SSPBUF,
2: The CKP bit can be set by software
another
setting the BF bit before the falling edge of
the ninth clock, the CKP bit will not be
cleared and clock stretching will not occur.
regardless of the state of the BF bit.
Clock Stretching for 7-bit Slave
Transmit Mode
Clock Stretching for 10-bit Slave
Transmit Mode
data
 2010 Microchip Technology Inc.
transfer
sequence
(see