PIC18LF14K22-I/ML Microchip Technology, PIC18LF14K22-I/ML Datasheet - Page 133

• Manufacturer Part Number: PIC18LF14K22-I/ML
• Description: IC PIC MCU FLASH 512KX16 20-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF14K22-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, MSSP, SPI, USART
• Maximum Clock Frequency: 32 KHz
• Number Of Programmable I/os: 18
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

13.4.8
In Sleep mode, all clock sources are disabled. Timer2
will not increment and the state of the module will not
change. If the ECCP pin is driving a value, it will con-
tinue to drive that value. When the device wakes up, it
will continue from this state. If Two-Speed Start-ups are
enabled, the initial start-up frequency from HFINTOSC
and the postscaler may not be stable immediately.
In PRI_IDLE mode, the primary clock will continue to
clock the ECCP module without change. In all other
power-managed modes, the selected power-managed
mode clock will clock Timer2. Other power-managed
mode clocks will most likely be different than the
primary clock frequency.
TABLE 13-3:
 2010 Microchip Technology Inc.
CCPR1H
CCPR1L
CCP1CON
ECCP1AS
INTCON
IPR1
IPR2
PIE1
PIE2
PIR1
PIR2
PR2
PWM1CON
RCON
TMR1H
TMR1L
TMR2
TMR3H
TMR3L
TRISC
T1CON
T2CON
T3CON
Legend:
Name
— = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
OPERATION IN POWER-MANAGED
MODES
Capture/Compare/PWM Register 1, High Byte
Capture/Compare/PWM Register 1, Low Byte
Timer2 Period Register
Timer1 Register, High Byte
Timer1 Register, Low Byte
Timer2 Register
Timer3 Register, High Byte
Timer3 Register, Low Byte
ECCPASE ECCPAS2
GIE/GIEH PEIE/GIEL
OSCFIP
OSCFIE
OSCFIF
TRISC7
PRSEN
P1M1
RD16
RD16
IPEN
Bit 7
—
—
—
—
REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
SBOREN
TRISC6
T1RUN
PDC6
P1M0
ADIP
ADIE
ADIF
Bit 6
C1IP
C1IE
C1IF
—
ECCPAS1
T1CKPS1
T3CKPS1
TMR0IE
TRISC5
DC1B1
PDC5
RCIP
RCIE
RCIF
C2IP
C2IE
Bit 5
C2IF
—
ECCPAS0
T1CKPS0
T3CKPS0
Preliminary
TRISC4
DC1B0
INT0IE
PDC4
TXIP
EEIP
TXIE
EEIE
EEIF
Bit 4
TXIF
RI
PIC18F1XK22/LF1XK22
T1OSCEN
13.4.8.1
If the Fail-Safe Clock Monitor is enabled, a clock failure
will force the device into the RC_RUN Power-Managed
mode and the OSCFIF bit of the PIR2 register will be
set. The ECCP will then be clocked from the internal
oscillator clock source, which may have a different
clock frequency than the primary clock.
See the previous section for additional details.
13.4.9
Both Power-on Reset and subsequent Resets will force
all ports to Input mode and the CCP registers to their
Reset states.
This forces the enhanced CCP module to reset to a
state compatible with the standard CCP module.
CCP1M3
T3CCP1
PSSAC1
TRISC3
RABIE
SSPIP
BCLIP
SSPIE
BCLIE
SSPIF
BCLIF
PDC3
Bit 3
TO
EFFECTS OF A RESET
CCP1M2
T1SYNC
T3SYNC
PSSAC0
TMR0IF
CCP1IP
CCP1IE
CCP1IF
TRISC2
Operation with Fail-Safe
Clock Monitor
PDC2
Bit 2
PD
—
—
—
TMR1CS
TMR3CS
CCP1M1
PSSBD1
TMR2IP
TMR3IP
TMR2IE
TMR3IE
TMR2IF
TMR3IF
TRISC1
INT0IF
PDC1
Bit 1
POR
TMR1ON
TMR3ON
CCP1M0
PSSBD0
TMR1IP
TMR1IE
TMR1IF
TRISC0
DS41365D-page 133
RABIF
PDC0
Bit 0
BOR
—
—
—
on page
Values
Reset
259
259
259
259
257
260
260
260
260
260
260
258
259
258
258
258
258
259
259
260
258
258
259