ATTINY261-20SU Atmel, ATTINY261-20SU Datasheet - Page 147
ATTINY261-20SU
Manufacturer Part Number
ATTINY261-20SU
Description
IC MCU AVR 2K FLASH 20MHZ 20SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY261-20SU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SPI, USI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 55 C
On-chip Adc
10 bit, 11 Channel
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATSTK505 - ADAPTER KIT FOR 14PIN AVR MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY261-20SU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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2588E–AVR–08/10
Figure 15-5. ADC Timing Diagram, Single Conversion
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. See
15-6. This assures a fixed delay from the trigger event to the start of conversion. In this mode,
the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger
source signal. Three additional CPU clock cycles are used for synchronization logic.
Figure 15-6. ADC Timing Diagram, Auto Triggered Conversion
In Free Running mode (see
conversion completes, while ADSC remains high.
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
Prescaler
Reset
1
MUX and REFS
Update
1
2
MUX and REFS
Update
2
3
Figure
Sample & Hold
3
4
Sample &
Hold
4
5
15-7), a new conversion will be started immediately after the
5
6
6
7
One Conversion
7
8
One Conversion
8
9
9
10
Conversion
Complete
10
Conversion
Complete
11
11
12
12
13
13
Sign and MSB of Result
LSB of Result
Sign and MSB of Result
Next Conversion
1
LSB of Result
2
Next Conversion
MUX and REFS
Update
1
Prescaler
Reset
3
Figure
2
147
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