AT90PWM3-16MQT Atmel, AT90PWM3-16MQT Datasheet - Page 25

• Manufacturer Part Number: AT90PWM3-16MQT
• Description: MCU AVR 8K FLASH 16MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM3-16MQT

• Package / Case: 32-QFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Speed: 16MHz
• Number Of I /o: 27
• Eeprom Size: 512 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Program Memory Size: 8KB (8K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: SPI, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.2
4317IS–AVR–01/08
AT90PWM2B/3B
15. PSC : Autolock mode
16. DALI : 17th bit detection
17. PSC : One ramp mode with PSC input mode 8
18. PSC : Desactivation of outputs in mode 14
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1. PSC : Double End-Of-Cycle Interrupt Request in Centered Mode
2. ADC : Conversion accuracy
3. DAC Driver linearity above 3.6V
The comparator output toggles at the comparator clock frequency when the voltage differ-
ence between both inputs is lower than the offset. This may occur when comparing signal
with small slew rate.
Work around:
This effect normally do not impact the PSC, as the transition is sampled once per PSC cycle
Be carefull when using the comparator as an interrupt source.
This mode is not properly handled when CLKPSC is different from CLK IO.
Work around:
With CLKPSC equals 64/32 MHz (CLKPLL), use LOCK mode
17th bit detection do not occurs if the signal arrives after the sampling point.
Workaround:
Use this feature only for sofware development and not in field conditions
The retriggering is not properly handled in this case.
Work around:
Do not program this case.
See “PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Disactivate Output” on
page 155.
Work around:
Do not use this mode to desactivate output if retrigger event do not occurs during On-Time.
PSC : Double End-Of-Cycle Interrupt Request in Centered Mode
ADC : Conversion accuracy
In centered mode, after the “expected” End-Of-Cycle Interrupt, a second unexpected Inter-
rupt occurs 1 PSC cycle after the previous interrupt.
Work around:
While CPU cycle is lower than PSC clock, the CPU sees only one interrupt request. For PSC
clock period greater than CPU cycle, the second interrupt request must be cleared by
software.
The conversion accuracy degrades when the ADC clock is 2 MHz.
Work around:
When a 10 bit conversion accuracy is required, use an ADC clock of 1 MHz or below.
At 2 Mhz the ADC can be used as a 7 bits ADC.
With 5V Vcc, the DAC driver linearity is poor when DAC output level is above Vcc-1V. At 5V,
DAC output for 1023 will be around 5V - 40mV.
Work around: .
AT90PWM2/3/2B/3B
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