AT90PWM3-16MQT Atmel, AT90PWM3-16MQT Datasheet - Page 15

• Manufacturer Part Number: AT90PWM3-16MQT
• Description: MCU AVR 8K FLASH 16MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM3-16MQT

• Package / Case: 32-QFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Speed: 16MHz
• Number Of I /o: 27
• Eeprom Size: 512 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Program Memory Size: 8KB (8K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: SPI, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4317IS–AVR–01/08
Mnemonics
MOVW
SWAP
BSET
BCLR
PUSH
ROR
MOV
ROL
ASR
SEC
SEN
SEH
LPM
LPM
LPM
SPM
OUT
POP
LSR
BST
BLD
CLC
CLN
SEZ
CLZ
SES
CLS
SEV
CLV
SET
CLT
CLH
LDD
LDD
LDS
STD
STD
STS
SBI
CBI
LSL
SEI
CLI
LDI
LD
LD
LD
LD
LD
LD
LD
LD
LD
ST
ST
ST
ST
ST
ST
ST
ST
ST
IN
Operands
Rd, Z+q
Rd,Y+q
Rd, X+
Rd, - X
Rd, Y+
Rd, - Y
Y+q,Rr
Z+q,Rr
Rd, Rr
Rd, Rr
Rd, Z+
X+, Rr
- X, Rr
Y+, Rr
- Y, Rr
Rd, Z+
Rd, -Z
Z+, Rr
Rd, K
Rd, X
Rd, Y
Rd, Z
-Z, Rr
Rd, Z
Rd, P
Rd, b
Rd, k
X, Rr
Y, Rr
P, Rr
Rr, b
Z, Rr
k, Rr
P,b
P,b
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rr
s
s
BIT AND BIT-TEST INSTRUCTIONS
DATA TRANSFER INSTRUCTIONS
MCU CONTROL INSTRUCTIONS
Load Program Memory and Post-Inc
Clear Twos Complement Overflow
Set Twos Complement Overflow.
Store Indirect with Displacement
Store Indirect with Displacement
Load Indirect with Displacement
Load Indirect with Displacement
Clear Half Carry Flag in SREG
Set Half Carry Flag in SREG
Rotate Right Through Carry
Bit Store from Register to T
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Rotate Left Through Carry
Bit load from T to Register
Move Between Registers
Pop Register from Stack
Clear Bit in I/O Register
Global Interrupt Disable
Load Direct from SRAM
Store Program Memory
Push Register on Stack
Global Interrupt Enable
Clear Signed Test Flag
Load Program Memory
Load Program Memory
Set Bit in I/O Register
Store Direct to SRAM
Arithmetic Shift Right
Set Signed Test Flag
Copy Register Word
Clear Negative Flag
Logical Shift Right
Set Negative Flag
Logical Shift Left
Clear T in SREG
Load Immediate
Clear Zero Flag
Set T in SREG
Description
Swap Nibbles
Set Zero Flag
Store Indirect
Store Indirect
Store Indirect
Load Indirect
Load Indirect
Load Indirect
Clear Carry
Flag Clear
Set Carry
Flag Set
Out Port
In Port
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Rd(n+1) ← Rd(n), Rd(0) ← 0
Rd(n) ← Rd(n+1), Rd(7) ← 0
Rd(n) ← Rd(n+1), n=0..6
Rd ← (X), X ← X + 1
Rd ← (Y), Y ← Y + 1
Rd+1:Rd ← Rr+1:Rr
X ← X - 1, Rd ← (X)
Y ← Y - 1, Rd ← (Y)
(X) ← Rr, X ← X + 1
(Y) ← Rr, Y ← Y + 1
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, Rd ← (Z)
X ← X - 1, (X) ← Rr
Y ← Y - 1, (Y) ← Rr
Rd ← (Z), Z ← Z+1
Z ← Z - 1, (Z) ← Rr
Rd ← (Z), Z ← Z+1
Rd ← STACK
SREG(s) ← 1
SREG(s) ← 0
STACK ← Rr
Rd ← (Y + q)
Rd ← (Z + q)
I/O(P,b) ← 1
I/O(P,b) ← 0
(Y + q) ← Rr
(Z + q) ← Rr
(Z) ← R1:R0
Operation
Rd(b) ← T
T ← Rr(b)
Rd ← (X)
Rd ← (Y)
Rd ← (k)
Rd ← (Z)
R0 ← (Z)
Rd ← (Z)
Rd ← Rr
Rd ← K
(X) ← Rr
(Y) ← Rr
(Z) ← Rr
(k) ← Rr
Rd ← P
P ← Rr
C ← 1
C ← 0
N ← 1
N ← 0
S ← 1
S ← 0
V ← 1
V ← 0
H ← 1
H ← 0
Z ← 1
Z ← 0
T ← 1
T ← 0
I ← 1
I ← 0
AT90PWM2/3/2B/3B
SREG(s)
SREG(s)
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Flags
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
C
C
N
N
S
S
V
V
H
H
T
Z
Z
T
T
I
I
#Clocks
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
1
1
2
2
-
15