PIC12CE519-04/SN Microchip Technology, PIC12CE519-04/SN Datasheet - Page 284

• Manufacturer Part Number: PIC12CE519-04/SN
• Description: IC MCU OTP 1KX12 W/EE 8SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12CE519-04/SN

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 1.5KB (1K x 12)
• Program Memory Type: OTP
• Eeprom Size: 16 x 8
• Ram Size: 41 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (3.9mm Width)
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING309-1046 - ADAPTER 8-SOIC TO 8-DIP309-1045 - ADAPTER 8-SOIC TO 8-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -

PICmicro MID-RANGE MCU FAMILY
Register 17-3:
DS31017A-page 17-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SSPCON2: SSP Control Register2
bit 7
GCEN: General Call Enable bit (In I
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
ACKSTAT: Acknowledge Status bit (In I
In master transmit mode:
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
ACKDT: Acknowledge Data bit (In I
In master receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a
receive.
1 = Not Acknowledge
0 = Acknowledge
ACKEN: Acknowledge Sequence Enable bit (In I
In master receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit AKDT data bit.
0 = Acknowledge sequence idle
RCEN: Receive Enable bit (In I
1 = Enables Receive mode for I
0 = Receive idle
PEN: Stop Condition Enable bit (In I
SCK release control
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition idle
RSEN: Repeated Start Condition Enabled bit (In I
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition idle.
SEN: Start Condition Enabled bit (In I
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition idle
Legend
R = Readable bit
U = Unimplemented bit, read as ‘0’
GCEN
R/W-0
Note:
Note:
Note:
Note:
Note:
Automatically cleared by hardware.
If the I
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
If the I
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
If the I
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
If the I
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
If the I
the SSPBUF may not be written (or writes to the SSPBUF are disabled).
ACKSTAT
R/W-0
2
2
2
2
2
C module is not in the idle mode, this bit may not be set (no spooling), and
C module is not in the idle mode, this bit may not be set (no spooling), and
C module is not in the idle mode, this bit may not be set (no spooling), and
C module is not in the idle mode, this bit may not be set (no spooling), and
C module is not in the idle mode, this bit may not be set (no spooling), and
W = Writable bit
ACKDT
R/W-0
Preliminary
2
2
C master mode only)
C
2
2
2
C master mode only)
C master mode only)
C slave mode only)
2
C master mode only)
ACKEN
R/W-0
2
C master mode only)
2
2
C master mode only)
- n = Value at POR reset
C master mode only)
RCEN
R/W-0
R/W-0
PEN
1997 Microchip Technology Inc.
R/W-0
RSEN
bit 0
R/W-0
SEN