EP9315-CB Cirrus Logic Inc, EP9315-CB Datasheet - Page 32

• Manufacturer Part Number: EP9315-CB
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CB

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1261

EP9315
Enhanced Universal Platform SOC Processor
IDE Interface
Register Transfers
32
Cycle time
Address valid to DIORn / DIOWn setup
DIORn / DIOWn pulse width 8-bit
DIORn / DIOWn recovery time
DIOWn data setup
DIOWn data hold
DIORn data setup
DIORn data hold
DIORn data high impedance state
DIORn / DIOWn to address valid hold
Read Data Valid to IORDY
active (if IORDY initially low after t
IORDY Setup time
IORDY Pulse Width
IORDY assertion to release
DIOWn assert to data valid
Note:
1. t
2. This parameter specifies the time from the negation edge of DIORn to the time that the data bus is released by the device.
3. The delay from the activation of DIORn or DIOWn until the state of IORDY is first sampled. If IORDY is inactive then the host
4. Timings based upon software control. See User’s Guide.
5. ATA / ATAPI standards prior to ATA / ATAPI-5 inadvertently specified an incorrect value for mode 2 time t
6. All IDE timing is based upon HCLK = 100 MHz.
negation time. A host implementation shall lengthen t
reported in the devices IDENTIFY DEVICE data. A device implementation shall support any legal host implementation.
shall wait until IORDY is active before the register transfer cycle is completed. If the device is not driving IORDY negated at
the t
negated at the time t
16-bit PIO value.
0
is the minimum total cycle time, t
A
after the activation of DIORn or DIOWn, then t
Parameter
A
)
A
after the activation of DIORn or DIOWn, then t
©
Copyright 2005 Cirrus Logic (All Rights Reserved)
(max)
(max)
(max)
(max)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
2
is the minimum DIORn / DIOWn assertion time, and t
(Notes 1, 4, 5)
(Note 1, 4)
(Note 1, 4)
(Note 2, 4)
(Note 3, 4)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
5
2
shall be met and t
and/or t
2i
Symbol
to ensure that t
t
t
DDV
t
t
RD
t
t
t
t
t
t
t
t
t
t
t
6z
2i
C
0
1
2
3
4
5
6
9
A
B
RD
RD
shall be met and t
is not applicable. If the device is driving IORDY
Mode 0
(in ns)
1250
600
290
70
60
20
30
20
35
10
0
0
0
0
5
-
is equal to or greater than the value
Mode 1
(in ns)
1250
2i
383
290
5
50
45
20
30
15
35
10
0
0
0
5
-
is the minimum DIORn / DIOWn
is not applicable.
Mode 2
(in ns)
1250
330
290
30
30
20
30
10
35
10
0
0
0
5
-
0
by utilizing the
Mode 3
(in ns)
1250
180
80
30
70
30
20
30
10
35
10
0
0
0
5
DS638PP4
Mode 4
(in ns)
1250
120
25
70
25
20
20
30
10
35
10
0
0
0
5