C8051F349-GQ Silicon Laboratories Inc, C8051F349-GQ Datasheet - Page 86

• Manufacturer Part Number: C8051F349-GQ
• Description: IC 8051 MCU FLASH 32K 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F34xr

Specifications of C8051F349-GQ

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: I2C, SMBus, SPI, UART, USB
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F340DK
• Minimum Operating Temperature: - 40 C
• For Use With: 336-1748 - ADAPTER TOOLSTICK FOR C8051F34X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1509

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
9.2.7. Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should not be set to logic l. Future product versions may use these bits to implement new features in which
case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of
the remaining SFRs are included in the sections of the datasheet associated with their corresponding sys-
tem function.
86
Bits7–0: DPL: Data Pointer Low.
Bits7–0: DPH: Data Pointer High.
Bits7–0: SP: Stack Pointer.
R/W
R/W
R/W
Bit7
Bit7
Bit7
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed memory.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed memory.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented
before every PUSH operation. The SP register defaults to 0x07 after reset.
R/W
R/W
R/W
Bit6
Bit6
Bit6
SFR Definition 9.2. DPH: Data Pointer High Byte
SFR Definition 9.1. DPL: Data Pointer Low Byte
R/W
R/W
R/W
Bit5
Bit5
Bit5
SFR Definition 9.3. SP: Stack Pointer
R/W
R/W
R/W
Bit4
Bit4
Bit4
Rev. 1.3
R/W
R/W
R/W
Bit3
Bit3
Bit3
R/W
R/W
R/W
Bit2
Bit2
Bit2
R/W
R/W
R/W
Bit1
Bit1
Bit1
R/W
R/W
R/W
Bit0
Bit0
Bit0
SFR Address:
SFR Address:
SFR Address:
00000000
00000000
00000111
Reset Value
Reset Value
Reset Value
0x83
0x81
0x82