C8051F349-GQ Silicon Laboratories Inc, C8051F349-GQ Datasheet - Page 273

• Manufacturer Part Number: C8051F349-GQ
• Description: IC 8051 MCU FLASH 32K 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F34xr

Specifications of C8051F349-GQ

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: I2C, SMBus, SPI, UART, USB
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F340DK
• Minimum Operating Temperature: - 40 C
• For Use With: 336-1748 - ADAPTER TOOLSTICK FOR C8051F34X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1509

23.2. C2 Pin Sharing
The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and
Flash programming functions may be performed. This is possible because C2 communication is typically
performed when the device is in the halt state, where all on-chip peripherals and user software are stalled.
In this halted state, the C2 interface can safely ‘borrow’ the C2CK (RST) and C2D (P3.0) pins. Note that
the C2D pin is shared on the 32-pin packages only (C8051F342/3/6/7/9/A/B). In most applications, exter-
nal resistors are required to isolate C2 interface traffic from the user application. A typical isolation configu-
ration is shown in Figure 23.1.
The configuration in Figure 23.1 assumes the following:
Additional resistors may be necessary depending on the specific application.
1. The user input (b) cannot change state while the target device is halted.
2. The RST pin on the target device is used as an input only.
Output (c)
RST (a)
Input (b)
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Figure 23.1. Typical C2 Pin Sharing
C2 Interface Master
Rev. 1.3
C2CK
C2D
C8051Fxxx
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