C8051F349-GQ Silicon Laboratories Inc, C8051F349-GQ Datasheet
C8051F349-GQ
Manufacturer Part Number
C8051F349-GQ
Description
IC 8051 MCU FLASH 32K 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F34xr
Specifications of C8051F349-GQ
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2.25 KB
Interface Type
I2C, SMBus, SPI, UART, USB
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F340DK
Minimum Operating Temperature
- 40 C
For Use With
336-1748 - ADAPTER TOOLSTICK FOR C8051F34X
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
336-1509
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F349-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F349-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Analog Peripherals
10-Bit ADC
Two Comparators
POR/Brown-out Detector
USB Function Controller
-
-
-
-
-
-
On-Chip Debug
-
-
-
-
Temperature Range: –40 to +85 °C
Development Kit: C8051F340DK
USB
USB specification 2.0 compliant
Full-speed (12 Mbps) or low-speed (1.5 Mbps) operation
Integrated clock recovery; no external crystal required for either full-
speed or low-speed operation
Supports eight flexible endpoints
Dedicated 1 kB USB buffer memory
Integrated transceiver; no external resistors required
On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
Provides breakpoints, single stepping
Inspect/modify memory, registers, and USB memory
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
C2CK/RST
VREG
VBUS
GND
VDD
D+
D-
Power-On
Regulator
Monitor
Voltage
Supply
Reset
C2D
XTAL1
XTAL2
Reset
Power
Net
System Clock Setup
Transceiver
Oscillator
Oscillator
Recovery
External
Full / Low
Internal
Debug / Programming
Clock
USB Peripheral
Speed
Controller Core
32 kB ISP FLASH
Program Memory
CIP-51 8051
256 Byte RAM
2 kB XRAM
Hardware
Copyright © 2009 by Silicon Laboratories
Low Freq.
1 kB RAM
Multiplier
Oscillator
Controller
Clock
USB, 25 MIPS, 32 kB Flash, 32-Pin Mixed-Signal MCU
SFR
Bus
High-Speed 8051 µC Core
-
-
-
Memory
-
-
Digital Peripherals
-
-
-
-
Clock Sources
-
-
-
Voltage Regulator
-
-
Operating Voltage: 2.7 to 5.25 V
Ordering Part Number
-
-
Timers 0, 1,
Analog Peripherals
PCA/WDT
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
Up to 25 MIPS throughput with 25 MHz Clock
Expanded interrupt handler
2304 bytes data RAM (256 + 2 kB)
32 kB Flash; in-system programmable in 512-byte sectors
25 port I/O; all are 5 V tolerant
Hardware SMBus™ (I
available concurrently
4 general-purpose 16-bit counter/timers
Programmable 16-bit counter array with 5 capture/compare modules
Internal oscillator: 0.25% accuracy with clock recovery enabled;
supports all USB and UART modes
External oscillator: Crystal, RC, C, or Clock
On-chip clock multiplier: up to 48 MHz
On-chip voltage regulator supports USB bus-powered operation
Regulator bypass mode supports USB self-powered operation
C8051F349-GQ, 32-Pin LQFP, 9x9 mm
C8051F349-GM, 32-Pin QFN, 5x5 mm
Digital Peripherals
UART0
SMBus
Port I/O Configuration
2, 3
SPI
Crossbar Control
2 Comparators
CP0
CP1
+
+
-
-
Crossbar
Decoder
Priority
2
C™ compatible), SPI™, and UART serial ports
Drivers
Drivers
Drivers
Drivers
Port 0
Port 1
Port 2
Port 3
C8051F349
2
2
P0.0
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4
P0.5
P0.6/CNVSTR
P0.7/VREF
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
4.8.2009
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