C8051F321-GM Silicon Laboratories Inc, C8051F321-GM Datasheet - Page 110

• Manufacturer Part Number: C8051F321-GM
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F321-GM

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: I2C/SMBus/SPI/UART/USB
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F320DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 10-bit or 17-ch x 10-bit
• No. Of I/o's: 21
• Ram Memory Size: 1280Byte
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1480 - DAUGHTER CARD TOOLSTCK C8051F321770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1449 - ADAPTER PROGRAM TOOLSTICK F321336-1260 - DEV KIT FOR C8051F320/F321
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1261

C8051F320/1
11.4. Flash Write and Erase Guidelines
Any system which contains routines which write or erase Flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating range of VDD, system clock frequency, or temperature. This accidental execution of Flash modi-
fying code can result in alteration of Flash memory contents causing a system failure that is only recover-
able by re-Flashing the code in the device.
To help prevent the accidental modification of Flash by firmware, the VDD Monitor must be enabled and
enabled as a reset source on C8051F32x devices for the Flash to be successfully modified. If either the
VDD Monitor or the VDD Monitor reset source is not enabled, a Flash Error Device Reset will be
generated when the firmware attempts to modify the Flash.
The following guidelines are recommended for any system that contains routines which write or erase
Flash from code.
11.4.1. VDD Maintenance and the VDD Monitor
110
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient
2. Make certain that the minimum VDD rise time specification of 1 ms is met. If the system cannot
3. Keep the on-chip VDD Monitor enabled and enable the VDD Monitor as a reset source as
4. As an added precaution, explicitly enable the VDD Monitor and enable the VDD Monitor as a
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a '1'. Areas
protection devices to the power supply to ensure that the supply voltages listed in the Absolute
Maximum Ratings table are not exceeded.
meet this rise time specification, then add an external VDD brownout circuit to the /RST pin of
the device that holds the device in reset until VDD reaches 2.7 V and re-asserts /RST if VDD
drops below 2.7 V.
early in code as possible. This should be the first set of instructions executed after the Reset
Vector. For 'C'-based systems, this will involve modifying the startup code added by the 'C'
compiler. See your compiler documentation for more details. Make certain that there are no
delays in software between enabling the VDD Monitor and enabling the VDD Monitor as a
reset source. Code examples showing this can be found in AN201, "Writing to Flash from
Firmware", available from the Silicon Laboratories web site.
reset source inside the functions that write and erase Flash memory. The VDD Monitor enable
instructions should be placed just after the instruction to set PSWE to a '1', but before the
Flash write or erase operation instruction.
operators and explicitly DO NOT use the bit-wise operators (such as AND or OR). For exam-
ple, "RSTSRC = 0x02" is correct, but "RSTSRC |= 0x02" is incorrect.
to check are initialization code which enables other reset sources, such as the Missing Clock
Detector or Comparator, for example, and instructions which force a Software Reset. A global
search on "RSTSRC" can quickly verify this.
Rev. 1.4