C8051F230-GQ Silicon Laboratories Inc, C8051F230-GQ Datasheet - Page 116

• Manufacturer Part Number: C8051F230-GQ
• Description: IC 8051 MCU 8K FLASH 48TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F2xxr

Specifications of C8051F230-GQ

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 48-TQFP, 48-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 32
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F2x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F226DK
• Minimum Operating Temperature: - 40 C
• No. Of I/o's: 32
• Ram Memory Size: 256Byte
• Cpu Speed: 25MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 48TQFP
• Device Core: 8051
• Family Name: C8051F2xx
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1242

C8051F2xx
116
Bits7–0: SCR7–SCR0: SPI Clock Rate
These bits determine the frequency of the SCK output when the SPI module is configured for master
Bits7–0: SPI0DAT: SPI0 Transmit and Receive Data.
SCR7
R/W
R/W
Bit7
Bit7
-
mode operation. The SCK clock frequency is a divided down version of the system clock,
and is given in the following equations:
fSCK = 0.5 x fSYSCLK / (SPI0CKR + 1), for 0 < SPI0CKR < 255,
The SPI0DAT register is used to transmit and receive SPI data. Writing data to SPI0DAT
places the data immediately into the shift register and initiates a transfer when in Master
Mode. A read of SPI0DAT returns the contents of the receive buffer.
SCR6
R/W
R/W
Bit6
Bit6
-
SFR Definition 15.3. SPI0CKR: SPI Clock Rate Register
SFR Definition 15.4. SPI0DAT: SPI Data Register
SCR5
R/W
R/W
Bit5
Bit5
-
SCR4
R/W
Bit4
R/W
Bit4
-
SCR3
Rev. 1.6
R/W
Bit3
R/W
Bit3
-
SCR2
R/W
Bit2
R/W
Bit2
-
SCR1
R/W
Bit1
R/W
Bit1
-
SCR0
R/W
Bit0
R/W
Bit0
-
SFR Address:
SFR Address:
Reset Value
Reset Value
00000000
00000000
0x9B
0x9D