C8051F332-GM Silicon Laboratories Inc, C8051F332-GM Datasheet - Page 198

• Manufacturer Part Number: C8051F332-GM
• Description: IC 8051 MCU 4KB FLASH 20QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F33xr

Specifications of C8051F332-GM

• Program Memory Type: FLASH
• Program Memory Size: 4KB (4K x 8)
• Package / Case: 20-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F330DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• No. Of I/o's: 17
• Ram Memory Size: 768Byte
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Package: 20QFN
• Device Core: 8051
• Family Name: C8051F33x
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1451 - ADAPTER PROGRAM TOOLSTICK F330
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1266

C8051F330/1/2/3/4/5
19.3.1. Watchdog Timer Operation
While the WDT is enabled:
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While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run
until the WDT is disabled. The PCA counter run control (CR) will read zero if the WDT is enabled but user
software has not enabled the PCA counter. If a match occurs between PCA0CPH2 and PCA0H while the
WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a write
of any value to PCA0CPH2. Upon a PCA0CPH2 write, PCA0H plus the offset held in PCA0CPL2 is loaded
into PCA0CPH2 (See Figure 19.10).
202
PCA counter is forced on.
Writes to PCA0L and PCA0H are not allowed.
PCA clock source bits (CPS2 – CPS0) are frozen.
PCA Idle control bit (CIDL) is frozen.
Module 2 is forced into software timer mode.
Writes to the Module 2 mode register (PCA0CPM2) are disabled.
PCA0CPL2
C
D
L
I
Figure 19.10. PCA Module 2 with Watchdog Timer Enabled
W
D
T
E
PCA0MD
W
D
C
L
K
PCA0CPH2
C
P
S
2
Write to
C
P
S
1
C
P
S
0
E
C
F
8-bit Adder
Enable
Adder
Enable
Rev. 1.7
PCA0CPH2
Comparator
PCA0H
8-bit
Match
PCA0L Overflow
Reset