DSPIC30F6010-30I/PF Microchip Technology, DSPIC30F6010-30I/PF Datasheet - Page 12

• Manufacturer Part Number: DSPIC30F6010-30I/PF
• Description: IC DSPIC MCU/DSP 144K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6010-30I/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 68
• Flash Memory Size: 144KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300019 - BOARD DEMO DSPICDEM 80L STARTERAC164314 - MODULE SKT FOR PM3 80PFDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRLAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F601030IPF

dsPIC30F6010
24. Module: 4x PLL Operation
EXAMPLE 11:
EXAMPLE 12:
EXAMPLE 13:
DS80195H-page 12
.include
...
DISI
BCLR
...
.include
...
__asm__ volatile (“DISI #0x1FFF”);
SRbits.IPL = 0x5;
DISICNT = 0x0;
#define DISI_PROTECT(X) {\
DISI_PROTECT(SRbits.IPL = 0x5);
When the 4x PLL mode of operation is selected,
the specified input frequency range of 4-10 MHz is
not fully supported.
When device V
frequency must be in the range of 4-5 MHz. When
device V
must be in the range of 4-6 MHz for both industrial
and extended temperature ranges.
Work around
1. Use 8x PLL or 16x PLL mode of operation and
2. Use the EC without PLL Clock mode with a
__asm__ volatile (“DISI #0x1FFF”);\
X;
DISICNT = 0; }
set final device clock speed using the
POST<1:0> oscillator postscaler control bits
(OSCCON<7:6>).
suitable
equivalent 4x PLL clock rate.
#2
IEC1, #INT1IE
; next instruction protected by DISI
DD
is 3.0-3.6V, the 4x PLL input frequency
clock
“p30fxxxx.inc”
“p30fxxxx.h”
USING DISI
RAISING CPU INTERRUPT PRIORITY LEVEL
USING MACRO
DD
is 2.5-3.0V, the 4x PLL input
frequency
; protect the disable of INT1
; disable interrupt 1
\
to
// safely modify the CPU IPL
obtain
// protect CPU IPL modification
// set CPU IPL to 5
// remove DISI protection
the
25. Module: Interrupt Controller – Sequential
When interrupt nesting is enabled (or NSTDIS
(INTCON1<15>) bit is ‘0’), the following sequence
of events will lead to an address error trap. The
generic terms “Interrupt 1” and “Interrupt 2” are
used to represent any two enabled dsPIC30F
interrupts.
1. Interrupt 1 processing begins.
2. Interrupt 1 is negated by user software by one
3. Interrupt 2 occurs with a priority higher than
Work around
The user may disable interrupt nesting or execute
a DISI instruction before modifying the CPU IPL
or Interrupt 1 setting. A minimum DISI value of 2
is required if the DISI is executed immediately
before the CPU IPL or Interrupt 1 is modified, as
shown in Example 11. If the MPLAB C30 compiler
is being used, one must inspect the Disassembly
Listing in the MPLAB IDE file to determine the
exact number of cycles to disable level 1-6
interrupts. One may use a large DISI value and
then set the DISICNT register to zero, as shown in
Example 12. A macro may also be used to perform
this task, as shown in Example 13.
of the following methods:
- CPU IPL is raised to Interrupt 1 IPL level or
- Interrupt 1 IPL is lowered to CPU IPL level or
- Interrupt 1 is disabled (Interrupt 1 IE bit set to
- Interrupt 1 flag is cleared
Interrupt 1.
higher or
lower or
‘0’) or
Interrupts
© 2008 Microchip Technology Inc.