DSPIC30F6010-30I/PF Microchip Technology, DSPIC30F6010-30I/PF Datasheet
DSPIC30F6010-30I/PF
Specifications of DSPIC30F6010-30I/PF
Available stocks
Related parts for DSPIC30F6010-30I/PF
DSPIC30F6010-30I/PF Summary of contents
Page 1
... Perform a “Connect” operation to the device (Debugger>Connect). Depending on the devel- opment tool used, the part number and Device Revision ID value appear in the Output window. Note: The Device and Revision ID values for the various dsPIC30F6010 silicon revisions are shown in Table 1. (1) Device ID 0x0188 the MPLAB ...
Page 2
... TABLE 2: SILICON ISSUE SUMMARY Item Module Feature Number Data Speed 1. EEPROM CPU Unsigned MAC 2. CPU MAC Class 3. Instructions with ±4 Address Modification CPU 4. DAW.b Instruction PSV — 5. Operations CPU Nested DO 6. Loops CPU Y Data Space 7. Interrupt Traps 8. Controller CPU 9. REPEAT ...
Page 3
... The PLL LOCK Status bit (OSCCON<5>) can occasionally get cleared and generate an oscillator failure trap even when the PLL is still locked and functioning correctly. An address error trap occurs in certain addressing modes when accessing the first four bytes of any PSV page. dsPIC30F6010 Affected Revisions B1 B2 ...
Page 4
... TABLE 2: SILICON ISSUE SUMMARY (CONTINUED) Item Module Feature Number 10-bit 36. Addressing 10-bit 37. Addressing Bus Collision 38. CAN RX Filters 3, 4 39. and 5 Flash Device Reset 40. Memory Interrupt IPC2 SFR 41. Controller Write Sequence QEI Timer Gated 42. Accumulation Mode QEI Timer Gated 43. Accumulation Mode ADC Current 44 ...
Page 5
... MAC class instructions. 2. Adding an accumulator write back (a dummy write back if needed) to either of the MAC class instructions. bits, POST 3. Do not use the + = address modification not prefetch data from Y space data. Affected Silicon Revisions B1 X integer dsPIC30F6010 of the instruction uses B2 X DS80459D-page 5 an ...
Page 6
... Module: CPU The Decimal Adjust instruction, DAW.b, may improperly clear the Carry bit, C (SR<0>), when executed. Work around Check the state of the Carry bit prior to executing the DAW.b instruction. If the Carry bit is set, set the Carry bit again after executing the DAW.b instruction ...
Page 7
... RAM register prior to performing the operations listed in Table 3. The work around for Example 2 is demonstrated in Example 3. © 2010 Microchip Technology Inc. Also, always use Work around 2 if the C compiler is used to generate code for dsPIC30F6010 devices. instructions are Examples of Incorrect Operation ADDC W0, [W1++], W2 ; ...
Page 8
... Module: CPU When using two DO loops in a nested fashion, terminating the inner-level DO loop by setting the EDT bit (CORCON<11>) will produce unexpected results. Specifically, the device may continue executing code within the outer DO loop forever. This erratum does not affect the operation of the MPLAB C30 compiler ...
Page 9
... Microchip Technology Inc. dsPIC30F6010 Work around If a math error trap occurs due to a catastrophic accumulator overflow, the overflow status flags, OA and/or OB (SR<15/14>), should be cleared within the trap handler routine. Subsequently, the MATHERR (INTCON1< ...
Page 10
... Module: CPU When interrupt nesting is enabled (or NSTDIS bit (INTCON1<15>) is ‘0’), the following sequence of events will lead to an address error trap: 1. REPEAT loop is active interrupt is generated during the execution of the REPEAT loop. 3. The CPU executes the Interrupt Service Routine (ISR) of the source causing the interrupt ...
Page 11
... Affected Silicon Revisions © 2010 Microchip Technology Inc. dsPIC30F6010 12. Module: Output Compare If the desired duty cycle is ‘0’ (OCxRS = 0), the module will generate a high level glitch The second problem is that on the next cycle after the glitch, the OC pin does not go high, or, in other words, it misses the next compare for any value written on OCxRS ...
Page 12
... Module: QEI For this release of silicon, the Quadrature Encoder Interface (QEI) module should not be operated in the Reset on Index Pulse mode. Work around None. Affected Silicon Revisions 15. Module: ADC Sampling multiple channels sequentially using any conversion trigger source other than the auto-convert feature requires SAMC bits to be non-zero ...
Page 13
... PWM3H/L and PWM4H/L) and any other chosen duty cycle. © 2010 Microchip Technology Inc. Observed Output PWM Low Low Output on PWM1L pin is shortened by dead time Low Low Low Output on PWM1H pin is shortened by dead time dsPIC30F6010 (1,2,3) Comments DS80459D-page 13 ...
Page 14
... Module: PWM Unexpected results may occur when the PWM pins are manually controlled using the OVDCON register and the OSYNC bit (PWMCON2<1>) is set. Work around Set OSYNC = 0 when the PWM pins are manually controlled using the OVDCON register. Affected Silicon Revisions ...
Page 15
... Work around For 5 volt applications, use a voltage regulator that ensures the range 4.75V to 5.5V, in order DD to achieve 30 MIPS operation. Affected Silicon Revisions (1) Max MIPS dsPIC30FXXX-30I dsPIC30FXXX-20I 30 20 — — dsPIC30F6010 at 30 MIPS DD remains between 4.75V DD dsPIC30FXXX-20E — 20 DS80459D-page 15 ...
Page 16
... Module: PLL When the 4x PLL mode of operation is selected, the specified input frequency range of 4 MHz-10 MHz is not fully supported. When device V is 2.5V-3.0V, the 4x PLL input DD frequency must be in the range of 4 MHz-5 MHz. When device V is 3.0V-3.6V, the 4x PLL input ...
Page 17
... SET_AND_SAVE_CPU_IPL (save_sr, 7);\ x; \ RESTORE_CPU_IPL (save_sr); } (void INTERRUPT_PROTECT (IEC0bits.U1TXIE=0); Note: If you are using a MPLAB C30 compiler version earlier than version 1.32, you may still use the macros by adding them to your application. Affected Silicon Revisions © 2010 Microchip Technology Inc. shown in dsPIC30F6010 DS80459D-page 17 ...
Page 18
... Module: PLL If 8x PLL mode is used, the input frequency range is 5 MHz-10 MHz instead of 4 MHz-10 MHz. Work around None PLL is used, make sure the input crystal or clock frequency is 5 MHz or greater. Affected Silicon Revisions EXAMPLE 15: unsigned int POSCNT_b15 = 0; unsigned int Motor_Position = 0; ...
Page 19
... GotoSleep( ) function call. This ensures that the device continues executing the correct code sequence after waking up from Sleep mode. Example 16 demonstrates the work around described above. ; Ensure flag is reset ; Return from Interrupt Service Routine dsPIC30F6010 the function call would be following the ...
Page 20
... Work around 2: Instead of executing a PWRSAV #0 instruction to put the device into Sleep mode, perform a clock switch to the 512 kHz Low-Power RC (LPRC) Oscillator with a 64:1 postscaler mode. This enables the device to operate at 0.002 MIPS, thereby significantly reducing consumption of the device. Similarly, instead of ...
Page 21
... Clear the I C receiver interrupt flag SI2CF back to step 1 to continue receiving incoming data bytes. © 2010 Microchip Technology Inc. dsPIC30F6010 Work around 2: Use this work around for applications in which the receiver interrupt is required. Assuming that the RBF and the I2COV flags in the I2CSTAT ...
Page 22
... Module: I/O If the user application enables the auto-baud feature in the UART module, the I/O pin multiplexed with the IC1 (Input Capture) pin cannot be used as a digital input. However, the external interrupt function (INT1) can be used. Work around None. Affected Silicon Revisions ...
Page 23
... SCL pins are shared with the UART and SPI pins, and the UART has higher precedence on the port latch pin. Affected Silicon Revisions dsPIC30F6010 module is enabled by setting the 2 C bus, and can cause 2 C module are set to values ‘1’ and ...
Page 24
... Module: CAN CAN Receive filters 3, 4 and 5 may not work for a given combination of instruction cycle speed and CAN bit time quanta. Work around Do not use CAN RX filters 3, 4 and 5. Instead, use filters 0, 1 and 2. Affected Silicon Revisions 40. Module: Flash Memory ...
Page 25
... ADC module by setting the ADC Module Disable bit in the corresponding Peripheral Module (PMDx) register, prior to executing a PWRSAV #0 instruction. Affected Silicon Revisions © 2010 Microchip Technology Inc. specifications Disable dsPIC30F6010 DS80459D-page 25 ...
Page 26
... Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS70119E): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 1. Module: DC Characteristics: I/O Pin Input ...
Page 27
... C), 30 (PWM), 31 (I/O (Timer), 34 (PLL), 35 (PSV Operations), 36-38 (I (CAN), 40 (Flash Memory) and 41 (Interrupt Controller). This document replaces the following errata documents: • DS80182, “dsPIC30F6010 Rev. B1 Silicon Errata” • DS80195, “dsPIC30F6010 Rev. B2 Silicon Errata” Rev B Document (8/2009) Updated silicon issue 25 (Interrupt Controller). ...
Page 28
... NOTES: DS80459D-page 28 © 2010 Microchip Technology Inc. ...
Page 29
... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 30
... Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2010 Microchip Technology Inc. 01/05/10 ...