PIC32MX440F512H-80I/PT Microchip Technology, PIC32MX440F512H-80I/PT Datasheet - Page 15

• Manufacturer Part Number: PIC32MX440F512H-80I/PT
• Description: IC PIC MCU FLASH 512K 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F512H-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 64-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 51
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

51. Module: DMA
52. Module: DMA
53. Module: PMP
54. Module: PMP
© 2010 Microchip Technology Inc.
If a DMA channel is suspend in the middle of a
transfer and an abort is issued, the channel’s
source, destination and cell pointer registers are
not reset.
Work around
Suspend the channel after the channel is aborted.
Affected Silicon Revisions
Turning the DMA module off while a transaction is
in progress may cause invalid instruction or data
fetches.
Work around
Ensure all DMA transactions are complete or abort
DMA transactions before turning off the DMA
module.
Affected Silicon Revisions
In Slave mode, the PMP interrupt is generated at
the start of the PMP write instead of at the end of
the write generated by the master. When the mas-
ter write occurs slowly in relation to the PB clock, it
is possible for the CPU to respond to the interrupt
before the data written by the master has been
latched.
Work around
Poll the PMSTAT register in the ISR to determine
when the data is available.
Affected Silicon Revisions
In Slave mode, the IBOV overflow flag may not
become set when an overflow occurs.
Work around
Do not allow the PMP buffer to overflow.
Affected Silicon Revisions
B2
B2
B2
B2
X
X
X
X
B3
B3
B3
B3
X
X
X
X
B4
B4
B4
B4
X
X
X
X
B6
B6
B6
B6
X
X
X
X
55. Module: DMA
56. Module: DMA
57. Module: SPI
The channel event bit may remain set if a transac-
tion completes as the user suspends the channel
by clearing the corresponding CHEN bit. This has
the effect that as soon as the channel is re-
enabled the event that should have been cleared
after the last transfer will still be pending and the
transfer will begin immediately after the channel is
re-enabled without waiting for an interrupt.
Work around
None.
Affected Silicon Revisions
DMA events are not detected during DMA sus-
pend. Any interrupt event that would initiate a DMA
transfer will not be captured while DMA is sus-
pended. When DMA is re-enabled the event will
have been lost.
Work around
Read the status of the peripheral interrupt flag. If
the interrupt has been asserted, force a DMA
transaction.
Affected Silicon Revisions
Reads of the SPIxBUF register when the SPIRBF
bit is clear will cause erroneous SPIRBF behavior.
Subsequent data in the buffer will not be reflected
by the SPIRBF bit.
Work around
Only read the SPIxBUF register when the SPIRBF
bit is set.
Affected Silicon Revisions
B2
B2
B2
X
X
X
PIC32MX3XX/4XX
B3
B3
B3
X
X
X
B4
B4
B4
X
X
X
B6
B6
B6
X
X
X
DS80440D-page 15