PIC24FJ256GB110-I/PT Microchip Technology, PIC24FJ256GB110-I/PT Datasheet - Page 183

• Manufacturer Part Number: PIC24FJ256GB110-I/PT
• Description: IC PIC MCU FLASH 256K 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256GB110-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 256KB (85.5K x 24)
• Package / Case: 100-TFQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 83
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 84
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM240011 - KIT STARTER MPLAB FOR PIC24F MCUMA240014 - MODULE PLUG-IN PIC24DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.2
To compute the Baud Rate Generator reload value, use
Equation 15-1.
EQUATION 15-1:
TABLE 15-1:
TABLE 15-2:
© 2008 Microchip Technology Inc.
Note 1:
Note 1:
Required System F
Slave Address
Note 1: Based on F
0000 000
0000 000
0000 001
0000 010
0000 011
0000 1xx
1111 1xx
1111 0xx
2:
2:
3:
2: These clock rate values are for guidance
Setting Baud Rate When
Operating as a Bus Master
100 kHz
100 kHz
100 kHz
400 kHz
400 kHz
400 kHz
400 kHz
1 MHz
1 MHz
1 MHz
I2CxBRG
F
or
Based on F
These clock rate values are for guidance only. The actual clock rate can be affected by various system
level parameters. The actual clock rate should be measured in its intended application.
The address bits listed here will never cause an address match, independent of address mask settings.
Address will be Acknowledged only if GCEN = 1.
Match on this address can only occur on the upper byte in 10-Bit Addressing mode.
SCL
PLL are disabled.
only. The actual clock rate can be affected
by various system level parameters. The
actual clock rate should be measured in
its intended application.
=
I
I
2
2
--------------------------------------------------------------------- -
I2CxBRG
C™ CLOCK RATES
C™ RESERVED ADDRESSES
=
R/W Bit
SCL
COMPUTING BAUD RATE
RELOAD VALUE
⎛
⎝
CY
CY
----------- -
F
0
1
x
x
x
x
x
x
F
SCL
CY
= F
= F
+ +
–
OSC
F
OSC
1
----------------------------- -
10 000 000
General Call Address
Start Byte
Cbus Address
Reserved
Reserved
HS Mode Master Code
Reserved
10-Bit Slave Upper Byte
CY
16 MHz
16 MHz
16 MHz
,
8 MHz
4 MHz
8 MHz
4 MHz
2 MHz
8 MHz
4 MHz
/2, Doze mode and PLL are disabled.
----------------------------- -
10 000 000
/2; Doze mode and
F
F
CY
CY
,
,
F
CY
,
⎞
⎠
(1,2)
(1,2)
–
1
PIC24FJ256GB110 FAMILY
Preliminary
(Decimal)
(2)
157
78
39
37
18
13
(1)
(3)
9
4
6
3
I2CxBRG Value
15.3
The I2CxMSK register (Register 15-3) designates
address bit positions as “don’t care” for both 7-Bit and
10-Bit Addressing modes. Setting a particular bit loca-
tion (= 1) in the I2CxMSK register causes the slave
module to respond whether the corresponding address
bit value is a ‘0’ or a ‘1’. For example, when I2CxMSK
is set to ‘00100000’, the slave module will detect both
addresses, ‘0000000’ and ‘0100000’.
To enable address masking, the IPMI (Intelligent
Peripheral Management Interface) must be disabled by
clearing the IPMIEN bit (I2CxCON<11>).
Note:
Description
(Hexadecimal)
Slave Address Masking
9D
4E
27
25
12
As a result of changes in the I
col, the addresses in Table 15-2 are
reserved and will not be acknowledged in
Slave mode. This includes any address
mask settings that include any of these
addresses.
D
9
4
6
3
Actual F
1.026 MHz
1.026 MHz
0.909 MHz
100 kHz
100 kHz
404 kHz
404 kHz
385 kHz
385 kHz
99 kHz
DS39897B-page 181
SCL
2
C™ proto-