PIC18F4525-I/ML Microchip Technology, PIC18F4525-I/ML Datasheet - Page 352

• Manufacturer Part Number: PIC18F4525-I/ML
• Description: IC MCU FLASH 24KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4525-I/ML

• Core Size: 8-Bit
• Program Memory Size: 48KB (24K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3968Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3986 B
• Interface Type: SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, 53275-917, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13 bit
• Package: 44QFN EP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNI3DB18F4620 - BOARD DAUGHTER ICEPIC3444-1001 - DEMO BOARD FOR PICMICRO MCU
• Lead Free Status / Rohs Status: Details

PIC18F2525/2620/4525/4620
FIGURE 26-14:
TABLE 26-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
DS39626E-page 350
Param.
71
71A
72
72A
73
73A
74
75
76
78
79
80
81
Note 1:
No.
Note:
(CKP = 0)
(CKP = 1)
SDI
SCK
SDO
SS
SCK
2:
TscH
TscL
TdiV2scH,
TdiV2scL
Tb2b
TscH2diL,
TscL2diL
TdoR
TdoF
TscR
TscF
TscH2doV,
TscL2doV
TdoV2scH,
TdoV2scL
Requires the use of Parameter #73A.
Only if Parameter #71A and #72A are used.
Refer to Figure 26-5 for load conditions.
Symbol
EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SCK Input High Time
(Slave mode)
SCK Input Low Time
(Slave mode)
Setup Time of SDI Data Input to SCK Edge
Last Clock Edge of Byte 1 to the 1st Clock Edge
of Byte 2
Hold Time of SDI Data Input to SCK Edge
SDO Data Output Rise Time PIC18FXXXX
SDO Data Output Fall Time
SCK Output Rise Time
(Master mode)
SCK Output Fall Time (Master mode)
SDO Data Output Valid after
SCK Edge
SDO Data Output Setup to SCK Edge
81
73
MSb In
MSb
74
71
75, 76
Characteristic
80
72
bit 6 - - - - - -1
bit 6 - - - -1
Continuous
Single Byte
Continuous
Single Byte
PIC18LFXXXX
PIC18FXXXX
PIC18LFXXXX
PIC18FXXXX
PIC18LFXXXX
LSb In
LSb
1.25 T
1.25 T
1.5 T
Min
T
40
40
20
CY
40
—
—
—
—
—
79
78
CY
CY
CY
+ 40
+ 30
+ 30
© 2008 Microchip Technology Inc.
Max Units
100
25
45
25
25
45
25
50
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 2)
V
V
V
Conditions
DD
DD
DD
= 2.0V
= 2.0V
= 2.0V