PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 87

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 5-5:
© 2009 Microchip Technology Inc.
T3CON
PSPCON
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
EECON2
EECON1
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
MEMCON
OSCTUNE
TRISJ
TRISH
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
LATJ
LATH
LATG
LATF
LATE
LATD
LATC
LATB
LATA
PORTJ
PORTH
PORTG
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’, q = value depends on condition, r = reserved bit, do not modify. Shaded cells
Note 1:
File Name
(6)
(6)
2:
3:
4:
5:
6:
7:
8:
9:
(6)
(6)
(6)
(6)
(5)
(5,7)
are unimplemented, read as ‘0’.
Bit 7 and bit 6 are cleared by user software or by a POR.
Bit 21 of the PC is only available in Serial Programming modes.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
Alternate names and definitions for these bits when the MSSP module is operating in I
These bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values shown
apply only to 100-pin devices.
These bits and/or registers are only available in 80-pin and 100-pin devices; in 64-pin devices, they are unimplemented and read as ‘0’. Reset
values are shown for 100-pin devices.
In Microcontroller mode, the bits in this register are unwritable and read as ‘0’.
PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as ‘0’.
Implemented in 100-pin devices in Microcontroller mode only.
EUSART1 Baud Rate Generator Register Low Byte
EUSART1 Receive Register
EUSART1 Transmit Register
Program Memory Control Register (not a physical register)
TRISG7
SSP2IP
SSP2IF
SSP2IE
TRISH7
TRISE7
TRISD7
TRISJ7
LATG7
PSPIP
PSPIE
LATH7
LATE7
LATD7
OSCFIP
OSCFIE
PSPIF
LATJ7
OSCFIF
TRISC7
TRISF7
TRISB7
PPST1
LATC7
RG7
EBDIS
LATF7
LATB7
RH7
CSRC
SPEN
RDPU
RJ7
RD16
Bit 7
IBF
—
—
(5)
(6)
(5)
REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED)
(9)
(9)
(9)
(5)
(6)
(5)
(6)
(5)
(5)
(5)
(5)
(5)
(6)
(5)
(6)
(5)
TRISH6
TRISG6
TRISE6
TRISD6
BCL2IP
BCL2IF
BCL2IE
TRISJ6
PLLEN
LATH6
LATG6
LATE6
LATD6
T3CCP2
LATJ6
TRISF6
TRISC6
TRISB6
LATF6
LATC6
LATB6
RH6
RG6
REPU
RJ6
CMIP
CMIF
CMIE
ADIP
ADIF
ADIE
Bit 6
OBF
RX9
TX9
—
—
—
(5)
(6)
(5)
(5)
(6)
(5)
(6)
(5)
(8)
(5)
(5)
(5)
(5)
(6)
(5)
(6)
(5)
TRISH5
TRISG5
TRISD5
T3CKPS1
TRISJ5
LATH5
LATG5
LATD5
RC2IP
RC2IF
RC2IE
LATJ5
TRISE5
TRISC5
TRISB5
TRISA5
TRISF5
PPST0
ETHIP
ETHIE
RC1IP
RC1IE
WAIT1
LATE5
LATC5
LATB5
RH5
RG5
SREN
ETHIF
RC1IF
LATF5
LATA5
RJ5
TXEN
IBOV
Bit 5
—
(6)
(6)
(5)
(6)
(6)
(6)
(6)
(6)
(5)
(5)
(6)
(6)
(5)
(5)
PSPMODE
TRISH4
TRISD4
T3CKPS0
TRISJ4
LATH4
LATD4
LATJ4
TX2IP
TX2IF
TX2IE
TRISG4
TRISE4
TRISC4
TRISB4
TRISA4
TRISF4
WAIT0
LATG4
LATE4
LATC4
LATB4
RH4
SYNC
CREN
TX1IP
TX1IE
LATF4
LATA4
FREE
TX1IF
PPRE
RJ4
Bit 4
RG4
r
r
r
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(5)
(6)
(6)
(5)
TRISH3
TRISG3
TRISD3
TRISJ3
LATH3
LATG3
LATD3
T3CCP1
WRERR
TMR4IP
TMR4IE
LATJ3
ADDEN
TMR4IF
SSP1IP
SSP1IE
TRISE3
TRISC3
TRISB3
TRISA3
SENDB
BCL1IP
BCL1IF
BCL1IE
SSP1IF
TRISF3
LATE3
LATC3
LATB3
RH3
RG3
LATF3
LATA3
RJ3
Bit 3
—
—
—
(5)
(6)
(6)
PIC18F97J60 FAMILY
(5)
(6)
(5)
(6)
(5)
(6)
(5)
(6)
TRISH2
TRISG2
TRISJ2
LATH2
LATG2
T3SYNC
LATJ2
CCP5IP
CCP5IF
CCP5IE
CCP1IP
CCP1IF
CCP1IE
TRISE2
TRISD2
TRISC2
TRISB2
TRISA2
TRISF2
WREN
LATE2
LATD2
LATC2
LATB2
RH2
RG2
BRGH
LATF2
LATA2
FERR
RJ2
Bit 2
—
—
—
—
—
—
(5)
(6)
(6)
(5)
(6)
(6)
(5)
(6)
(6)
2
C™ Slave mode.
TRISH1
TRISG1
TRISJ1
TMR3CS
LATH1
LATG1
TMR3IP
TMR3IE
TMR2IP
TMR2IE
LATJ1
CCP4IP
CCP4IF
CCP4IE
TMR3IF
TMR2IF
TRISE1
TRISD1
TRISC1
TRISB1
TRISA1
TRISF1
LATE1
LATD1
LATC1
LATB1
RH1
RG1
OERR
LATF1
LATA1
TRMT
RJ1
WM1
Bit 1
WR
—
—
(5)
(6)
(6)
(5)
(6)
(6)
(5)
(6)
(6)
TRISH0
TRISG0
TRISF0
TMR3ON
TRISJ0
LATH0
LATG0
LATF0
TMR1IP
TMR1IE
LATJ0
CCP3IP
CCP3IF
CCP3IE
CCP2IP
CCP2IF
CCP2IE
TMR1IF
TRISE0
TRISD0
TRISC0
TRISB0
TRISA0
LATE0
LATD0
LATC0
LATB0
RH0
RG0
LATA0
RX9D
RJ0
TX9D
WM0
Bit 0
—
—
—
(5)
(6)
(6)
(5)
(6)
(5)
(6)
(5)
(6)
(5)
(6)
0000 0000
0000 ----
0000 0000
0000 0000
xxxx xxxx
0000 0010
0000 000x
---- ----
---0 x00-
1111 1111
0000 0000
0000 0000
1111 1-11
0000 0-00
0000 0-00
1111 1111
0000 0000
0000 0000
0-00 --00
0000 ----
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
--11 1111
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
00xx xxxx
xxxx xxxx
0000 xxxx
111x xxxx
POR, BOR
Values on
DS39762E-page 87
Details on
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65, 319
65, 310
65, 310
65, 100
65, 101
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65, 132
65, 134
65, 128
65, 131
65, 110
65, 162
65, 160
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65, 155
65, 153
65, 150
65, 147
65, 144
65, 141
65, 162
65, 160
66, 158
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66, 147
66, 144
66, 141
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Page:
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