PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet
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... High-Performance, © 2009 Microchip Technology Inc. PIC18F97J60 Family 1-Mbit Flash Microcontrollers Data Sheet with Ethernet DS39762E ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Address Capability Mbytes • 8-Bit or 16-Bit Interface • 12-Bit, 16-Bit and 20-Bit Addressing modes © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Peripheral Highlights: • High-Current Sink/Source: 25 mA/ PORTB and PORTC • Five Timer modules (Timer0 to Timer4) • Four External Interrupt pins • ...
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... PIC18F97J60 FAMILY Flash SRAM Ethernet Program Data TX/RX Device Memory Memory Buffer (bytes) (bytes) (bytes) PIC18F66J60 64K 3808 8192 PIC18F66J65 96K 3808 8192 PIC18F67J60 128K 3808 8192 PIC18F86J60 64K 3808 8192 PIC18F86J65 96K 3808 8192 PIC18F87J60 128K 3808 8192 PIC18F96J60 64K ...
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... TQFP RE1/P2C 1 RE0/P2D 2 RB0/INT0/FLT0 3 RB1/INT1 4 RB2/INT2 5 6 RB3/INT3 MCLR 7 RG4/CCP5/P1D DDCORE CAP RF7/SS1 11 RF6/AN11 12 RF5/AN10/CV 13 REF RF4/AN9 14 RF3/AN8 15 RF2/AN7/C1OUT © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY PIC18F66J60 41 PIC18F66J65 40 PIC18F67J60 DDRX TPIN+ TPIN- V SSRX RB4/KBI0 RB5/KBI1 RB6/KBI2/PGC V SS OSC2/CLKO OSC1/CLKI V DD ...
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... PIC18F97J60 FAMILY Pin Diagrams (Continued) 80-Pin TQFP 80 79 RH2 1 RH3 2 RE1/P2C 3 RE0/P2D 4 5 RB0/INT0/FLT0 6 RB1/INT1 RB2/INT2 7 RB3/INT3 8 MCLR 9 RG4/CCP5/P1D DDCORE CAP RF7/SS1 13 RF6/AN11 14 RF5/AN10/CV 15 REF RF4/AN9 16 RF3/AN8 17 RF2/AN7/C1OUT 18 (2) 19 RH7/AN15/P1B (2) 20 RH6/AN14/P1C Note 1: The ECCP2/P2A pin placement depends on the CCP2MX Configuration bit setting. ...
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... RF3/AN8 22 RF2/AN7/C1OUT 23 (2) 24 RH7/AN15/P1B (2) RH6/AN14/P1C 25 Note 1: The ECCP2/P2A pin placement depends on the CCP2MX Configuration bit and Processor mode settings. 2: P1B, P1C, P3B and P3C pin placement depends on the ECCPMX Configuration bit setting. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY PIC18F96J60 64 PIC18F96J65 ...
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... PIC18F97J60 FAMILY Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Oscillator Configurations ............................................................................................................................................................ 43 3.0 Power-Managed Modes ............................................................................................................................................................. 49 4.0 Reset .......................................................................................................................................................................................... 57 5.0 Memory Organization ................................................................................................................................................................. 71 6.0 Flash Program Memory .............................................................................................................................................................. 99 7.0 External Memory Bus ............................................................................................................................................................... 109 8 Hardware Multiplier.......................................................................................................................................................... 121 9.0 Interrupts .................................................................................................................................................................................. 123 10.0 I/O Ports ................................................................................................................................................................................... 139 11.0 Timer0 Module ......................................................................................................................................................................... 167 12 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY DS39762E-page 9 ...
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... PIC18F97J60 FAMILY NOTES: DS39762E-page 10 © 2009 Microchip Technology Inc. ...
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... Core Features 1.1.1 OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F97J60 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These options include: • Two Crystal modes, using crystals or ceramic resonators. • Two External Clock modes, offering the option of a divide-by-4 clock output. • ...
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... DS39762E-page 12 1.3 Details on Individual Family Members Devices in the PIC18F97J60 family are available in 64-pin, 80-pin and 100-pin packages. Block diagrams for the three groups are shown in Figure 1-1, C™ (Master Figure 1-2 and Figure 1-3. The devices are differentiated from each other in four ways: 1 ...
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... TABLE 1-1: DEVICE FEATURES FOR THE PIC18F97J60 FAMILY (64-PIN DEVICES) Features Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Interrupt Sources I/O Ports I/O Pins Timers Capture/Compare/PWM Modules Enhanced Capture/Compare/PWM Modules Serial Communications Ethernet Communications (10Base-T) Parallel Slave Port Communications (PSP) ...
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... PIC18F97J60 FAMILY TABLE 1-3: DEVICE FEATURES FOR THE PIC18F97J60 FAMILY ( Features Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Interrupt Sources I/O Ports I/O Pins Timers Capture/Compare/PWM Modules Enhanced Capture/Compare/PWM Modules Serial Communications Ethernet Communications (10Base-T) Parallel Slave Port Communications (PSP) ...
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... Timer0 10-Bit ECCP1 ECCP2 Note 1: See Table 1-4 for I/O port pin descriptions. 2: BOR functionality is provided when the on-board voltage regulator is enabled. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Data Bus<8> Data Latch 8 8 Data Memory (3808 Bytes) PCLATU PCLATH Address Latch ...
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... PIC18F97J60 FAMILY FIGURE 1-2: PIC18F86J60/86J65/87J60 (80-PIN) BLOCK DIAGRAM Table Pointer<21> inc/dec logic 21 20 Address Latch Program Memory (64, 96, 128 Kbytes) Data Latch 8 Table Latch ROM Latch Instruction Bus <16> Instruction Decode & Power-up Timing OSC2/CLKO Generation OSC1/CLKI Oscillator Start-up Timer INTRC ...
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... ECCP1 ECCP2 ECCP3 Note 1: See Table 1-6 for I/O port pin descriptions. 2: BOR functionality is provided when the on-board voltage regulator is enabled. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Data Latch 8 8 Data Memory (3808 Bytes) PCLATU PCLATH Address Latch PCU ...
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... PIC18F97J60 FAMILY TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS Pin Number Pin Name TQFP MCLR 7 OSC1/CLKI 39 OSC1 CLKI OSC2/CLKO 40 OSC2 CLKO RA0/LEDA/AN0 24 RA0 LEDA AN0 RA1/LEDB/AN1 23 RA1 LEDB AN1 RA2/AN2 REF RA2 AN2 V - REF RA3/AN3 REF RA3 AN3 V + REF RA4/T0CKI 28 RA4 T0CKI ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Pin Buffer Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. I/O TTL Digital I/O ...
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... PIC18F97J60 FAMILY TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RC0/T1OSO/T13CKI 30 RC0 T1OSO T13CKI RC1/T1OSI/ECCP2/P2A 29 RC1 T1OSI ECCP2 P2A RC2/ECCP1/P1A 33 RC2 ECCP1 P1A RC3/SCK1/SCL1 34 RC3 SCK1 SCL1 RC4/SDI1/SDA1 35 RC4 SDI1 SDA1 RC5/SDO1 36 RC5 SDO1 RC6/TX1/CK1 31 RC6 TX1 ...
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... RD2/CCP4/P3D 58 RD2 CCP4 P3D Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Pin Buffer Type Type PORTD is a bidirectional I/O port. I/O ST Digital I/O. O — ECCP1 PWM output B. I/O ST Digital I/O ...
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... PIC18F97J60 FAMILY TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RE0/P2D 2 RE0 P2D RE1/P2C 1 RE1 P2C RE2/P2B 64 RE2 P2B RE3/P3C 63 RE3 P3C RE4/P3B 62 RE4 P3B RE5/P1C 61 RE5 P1C Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels ...
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... AN11 RF7/SS1 11 RF7 SS1 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Pin Buffer Type Type PORTF is a bidirectional I/O port. I/O ST Digital I/O. I Analog Analog input 6. O — ...
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... PIC18F97J60 FAMILY TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RG4/CCP5/P1D 8 RG4 CCP5 P1D V 9, 25, 41 26, 38 ENVREG DDCORE CAP V DDCORE V CAP V 55 SSPLL V 54 DDPLL V 52 SSTX V 49 DDTX V 45 SSRX V 48 DDRX RBIAS 53 TPOUT+ 51 TPOUT- ...
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... Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Pin Buffer Type Type I ST Master Clear (Reset) input. This pin is an active-low Reset to the device ...
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... PIC18F97J60 FAMILY TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RB0/INT0/FLT0 5 RB0 INT0 FLT0 RB1/INT1 6 RB1 INT1 RB2/INT2 7 RB2 INT2 RB3/INT3 8 RB3 INT3 RB4/KBI0 54 RB4 KBI0 RB5/KBI1 53 RB5 KBI1 RB6/KBI2/PGC 52 RB6 KBI2 PGC RB7/KBI3/PGD 47 RB7 KBI3 PGD ...
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... Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port. ...
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... PIC18F97J60 FAMILY TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RD0 72 RD1 69 RD2 68 RE0/P2D 4 RE0 P2D RE1/P2C 3 RE1 P2C RE2/P2B 78 RE2 P2B RE3/P3C 77 RE3 (2) P3C RE4/P3B 76 RE4 (2) P3B RE5/P1C 75 RE5 (2) P1C RE6/P1B 74 RE6 (2) P1B RE7/ECCP2/P2A 73 RE7 (3) ECCP2 ...
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... Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Pin Buffer Type Type PORTF is a bidirectional I/O port. ...
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... PIC18F97J60 FAMILY TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RG0/ECCP3/P3A 56 RG0 ECCP3 P3A RG1/TX2/CK2 55 RG1 TX2 CK2 RG2/RX2/DT2 42 RG2 RX2 DT2 RG3/CCP4/P3D 41 RG3 CCP4 P3D RG4/CCP5/P1D 10 RG4 CCP5 P1D Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels ...
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... Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 3: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 4: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Pin Buffer Type Type PORTH is a bidirectional I/O port. ...
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... PIC18F97J60 FAMILY TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RJ4 39 RJ5 40 V 11, 31, 51 32, 48 ENVREG DDCORE CAP V DDCORE V CAP V 67 SSPLL V 66 DDPLL V 64 SSTX V 61 DDTX V 57 SSRX V 60 DDRX RBIAS 65 TPOUT+ 63 TPOUT- 62 TPIN+ 59 TPIN- ...
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... Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Pin Buffer Type Type I ST Master Clear (Reset) input. This pin is an active-low Reset to the device ...
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... PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RB0/INT0/FLT0 5 RB0 INT0 FLT0 RB1/INT1 6 RB1 INT1 RB2/INT2 7 RB2 INT2 RB3/INT3/ECCP2/P2A 8 RB3 INT3 (1) ECCP2 (1) P2A RB4/KBI0 69 RB4 KBI0 RB5/KBI1 68 RB5 KBI1 RB6/KBI2/PGC 67 RB6 KBI2 PGC RB7/KBI3/PGD 57 RB7 ...
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... Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port. ...
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... PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RD0/AD0/PSP0 92 RD0 AD0 PSP0 RD1/AD1/PSP1 91 RD1 AD1 PSP1 RD2/AD2/PSP2 90 RD2 AD2 PSP2 RD3/AD3/PSP3 89 RD3 AD3 PSP3 RD4/AD4/PSP4/SDO2 88 RD4 AD4 PSP4 SDO2 RD5/AD5/PSP5/ 87 SDI2/SDA2 RD5 AD5 PSP5 SDI2 ...
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... Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Pin Buffer Type Type PORTE is a bidirectional I/O port. ...
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... PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RF0/AN5 12 RF0 AN5 RF1/AN6/C2OUT 28 RF1 AN6 C2OUT RF2/AN7/C1OUT 23 RF2 AN7 C1OUT RF3/AN8 22 RF3 AN8 RF4/AN9 21 RF4 AN9 RF5/AN10/CV 20 REF RF5 AN10 CV REF RF6/AN11 19 RF6 AN11 RF7/SS1 18 RF7 ...
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... Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Pin Buffer Type Type PORTG is a bidirectional I/O port. ...
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... PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RH0/A16 99 RH0 A16 RH1/A17 100 RH1 A17 RH2/A18 1 RH2 A18 RH3/A19 2 RH3 A19 RH4/AN12/P3C 27 RH4 AN12 (5) P3C RH5/AN13/P3B 26 RH5 AN13 (5) P3B RH6/AN14/P1C 25 RH6 AN14 (5) P1C RH7/AN15/P1B 24 RH7 ...
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... Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Pin Buffer Type Type PORTJ is a bidirectional I/O port. ...
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... PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP 15, 36, 40, SS 60, 65 17, 37, 59 ENVREG DDCORE CAP V DDCORE V CAP V 82 SSPLL V 81 DDPLL V 79 SSTX V 76 DDTX V 72 SSRX V 75 DDRX RBIAS 80 TPOUT+ 78 TPOUT- 77 TPIN+ 74 TPIN- ...
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... Enable T1OSI Oscillator Note 1: See Table 2-2 for OSCTUNE register configurations and their corresponding frequencies. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 2.2 Oscillator Types The PIC18F97J60 family of devices can be operated in five different oscillator modes High-Speed Crystal/Resonator 2. HSPLL High-Speed Crystal/Resonator with Software PLL Control 3 ...
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... PIC18F97J60 FAMILY 2.3 Crystal Oscillator/Ceramic Resonators (HS Modes HSPLL Oscillator modes, a crystal is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 2-2 shows the pin connections. The oscillator design requires the use of a crystal that is rated for parallel resonant operation. Note: Use of a crystal rated for series resonant operation may give a frequency out of the crystal manufacturer’ ...
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... Internal Oscillator Block The PIC18F97J60 family of devices includes an internal oscillator source (INTRC) which provides a nominal 31 kHz output. The INTRC is enabled on device power-up and clocks the device during its configuration cycle until it enters operating mode. INTRC is also enabled selected as the device clock source or if any of the following are enabled: • ...
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... The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F97J60 family devices are shown in Figure 2-1. See Section 24.0 “Special Features of the CPU” for Configuration register details. ...
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... Internal oscillator Note 1: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY The IDLEN bit determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed. ...
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... FOSC2. 2.7.2 OSCILLATOR TRANSITIONS PIC18F97J60 family devices contain circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source ...
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... POWER-MANAGED MODES The PIC18F97J60 family devices provide the ability to manage power consumption by simply managing clock- ing to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. For the sake of managing power in an application, there are three primary modes of operation: • ...
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... PIC18F97J60 FAMILY 3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Two bits indicate the current clock source and its ...
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... OST (1) T PLL Clock Output CPU Clock Peripheral Clock Program Counter SCS1:SCS0 bits Changed Note 1024 (approx). These intervals are not shown to scale. OST OSC PLL © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY n-1 n Clock Transition (1) T PLL 1 2 n-1 n Clock ...
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... PIC18F97J60 FAMILY 3.2.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator; the primary clock is shut down. This mode provides the best power conser- vation of all the Run modes while still executing code. It works well for user applications which are not highly timing sensitive or do not require high-speed clocks at all times ...
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... These intervals are not shown to scale. OST OSC PLL © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 3.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to ‘ ...
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... PIC18F97J60 FAMILY 3.4.1 PRI_IDLE MODE This mode is unique among the three low-power Idle modes in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “ ...
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... This delay is required for the CPU to prepare for execu- tion. Instruction execution resumes on the first clock cycle following this delay. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 3.5.2 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs ...
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... PIC18F97J60 FAMILY NOTES: DS39762E-page 56 © 2009 Microchip Technology Inc. ...
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... RESET The PIC18F97J60 family of devices differentiates between various kinds of Reset: a) MCLR Reset during normal operation b) MCLR Reset during power-managed modes c) Power-on Reset (POR) d) Brown-out Reset (BOR) e) Configuration Mismatch (CM) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset i) Watchdog Timer (WDT) Reset during execution ...
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... PIC18F97J60 FAMILY REGISTER 4-1: RCON: RESET CONTROL REGISTER R/W-0 U-0 R/W-1 IPEN — CM bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 Unimplemented: Read as ‘ ...
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... POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any Power-on Reset. 4.4 Brown-out Reset (BOR) The PIC18F97J60 family of devices incorporates a simple BOR function when the internal regulator is enabled (ENVREG pin is tied Any drop ...
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... Power-on Reset process. The PWRT is always enabled. The main function is to ensure that the device voltage is stable before code is executed. The Power-up Timer (PWRT) of the PIC18F97J60 fam- ily devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048 x 32 μ ...
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... TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 4-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY T PWRT , V RISE > 3. PWRT ): CASE PWRT DS39762E-page 61 ...
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... PIC18F97J60 FAMILY 4.7 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up since this is viewed as the resumption of normal operation ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY MCLR Reset, WDT Reset, Power-on Reset, RESET Instruction, Brown-out Reset Stack Resets, ...
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... PIC18F97J60 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices STATUS PIC18F6XJ6X PIC18F8XJ6X TMR0H PIC18F6XJ6X PIC18F8XJ6X TMR0L PIC18F6XJ6X PIC18F8XJ6X T0CON PIC18F6XJ6X PIC18F8XJ6X OSCCON PIC18F6XJ6X PIC18F8XJ6X ECON1 PIC18F6XJ6X PIC18F8XJ6X WDTCON PIC18F6XJ6X PIC18F8XJ6X (4) RCON PIC18F6XJ6X PIC18F8XJ6X TMR1H PIC18F6XJ6X PIC18F8XJ6X TMR1L ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY MCLR Reset, WDT Reset, Power-on Reset, RESET Instruction, Brown-out Reset Stack Resets, ...
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... PIC18F97J60 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices LATG PIC18F6XJ6X PIC18F8XJ6X PIC18F6XJ6X PIC18F8XJ6X PIC18F6XJ6X PIC18F8XJ6X LATF PIC18F6XJ6X PIC18F8XJ6X PIC18F6XJ6X PIC18F8XJ6X LATE PIC18F6XJ6X PIC18F8XJ6X PIC18F6XJ6X PIC18F8XJ6X LATD PIC18F6XJ6X PIC18F8XJ6X PIC18F6XJ6X PIC18F8XJ6X LATC PIC18F6XJ6X PIC18F8XJ6X LATB PIC18F6XJ6X PIC18F8XJ6X ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY MCLR Reset, WDT Reset, Power-on Reset, RESET Instruction, Brown-out Reset Stack Resets, ...
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... PIC18F97J60 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices ETXNDH PIC18F6XJ6X PIC18F8XJ6X ETXNDL PIC18F6XJ6X PIC18F8XJ6X ETXSTH PIC18F6XJ6X PIC18F8XJ6X ETXSTL PIC18F6XJ6X PIC18F8XJ6X EWRPTH PIC18F6XJ6X PIC18F8XJ6X EWRPTL PIC18F6XJ6X PIC18F8XJ6X EPKTCNT PIC18F6XJ6X PIC18F8XJ6X ERXFCON PIC18F6XJ6X PIC18F8XJ6X EPMOH PIC18F6XJ6X PIC18F8XJ6X EPMOL ...
Page 69
... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY MCLR Reset, WDT Reset, Power-on Reset, RESET Instruction, Brown-out Reset Stack Resets, ...
Page 70
... PIC18F97J60 FAMILY NOTES: DS39762E-page 70 © 2009 Microchip Technology Inc. ...
Page 71
... NOP instruction). The entire PIC18F97J60 family offers three sizes of on-chip Flash program memory, from 64 Kbytes (up to 32,764 single-word instructions) to 128 Kbytes (65,532 single-word instructions). The program mem- ory maps for individual family members are shown in Figure 5-1 ...
Page 72
... CONFIG1 CONFIG3, are used; CONFIG4 is reserved. The actual addresses of the Flash Configuration Words for devices in the PIC18F97J60 family are shown in Table 5-1. Their location in the memory map is shown with the other memory vectors in Figure 5-2. Additional details on the device Configuration Words are provided in Section 24.1 “ ...
Page 73
... Unimplemented: Read as ‘0’ Note 1: Implemented on 100-pin devices only. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY • The Extended Microcontroller Mode allows access to both internal and external program memories as a single block. The device can access its entire on-chip program memory. Above this, the device accesses external program memory up to the 2-Mbyte program space limit ...
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... In practical terms, this means addresses in the external memory device below the top of on-chip memory are unavailable. FIGURE 5-3: MEMORY MAPS FOR PIC18F97J60 FAMILY PROGRAM MEMORY MODES (1) Microcontroller Mode Extended Microcontroller Mode On-Chip ...
Page 75
... Microchip Technology Inc. PIC18F97J60 FAMILY The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers ...
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... PIC18F97J60 FAMILY 5.1.6.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 5-2) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bit. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack ...
Page 77
... SUB1 • RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 5.1.8 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...
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... PIC18F97J60 FAMILY 5.2 PIC18 Instruction Cycle 5.2.1 CLOCKING SCHEME The microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the program counter is incremented on every Q1. The instruction is fetched from the program memory and latched into the Instruction Register (IR) during Q4 ...
Page 79
... ADDWF © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY The CALL and GOTO instructions have the absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. ...
Page 80
... RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of addressable memory. The memory space is divided into 16 banks that contain 256 bytes each. All of the PIC18F97J60 family devices implement all available banks and pro- vide 3808 bytes of data memory available to the user. ...
Page 81
... FIGURE 5-7: DATA MEMORY MAP FOR PIC18F97J60 FAMILY DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh 00h = 0010 Bank 2 FFh 00h = 0011 Bank 3 FFh 00h = 0100 Bank 4 FFh 00h = 0101 Bank 5 FFh 00h = 0110 Bank 6 FFh 00h = 0111 Bank 7 ...
Page 82
... PIC18F97J60 FAMILY FIGURE 5-8: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) (1) BSR (2) Bank Select Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction. ...
Page 83
... Bank 15 (F60h to FFFh). These SFRs can be classified into two sets: those associated with the “core” device functionality (ALU, Resets and interrupts) and those related to the peripheral functions. The TABLE 5-3: SPECIAL FUNCTION REGISTER MAP FOR PIC18F97J60 FAMILY DEVICES Address Name Address FFFh ...
Page 84
... PIC18F97J60 FAMILY 5.3.5 ETHERNET SFRs In addition to the standard SFR set in Bank 15, members of the PIC18F97J60 family have a second set of SFRs. This group, associated exclusively with the Ethernet module, occupies the top half of Bank 14 (E80h to EFFh). TABLE 5-4: ETHERNET SFR MAP FOR PIC18F97J60 FAMILY DEVICES ...
Page 85
... TABLE 5-5: REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) File Name Bit 7 Bit 6 Bit 5 TOSU — — — TOSH Top-of-Stack Register High Byte (TOS<15:8>) TOSL Top-of-Stack Register Low Byte (TOS<7:0>) (1) (1) STKPTR STKFUL STKUNF — PCLATU — — bit 21 PCLATH Holding Register for PC<15:8> ...
Page 86
... PIC18F97J60 FAMILY TABLE 5-5: REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 STATUS — — — TMR0H Timer0 Register High Byte TMR0L Timer0 Register Low Byte T0CON TMR0ON T08BIT T0CS OSCCON IDLEN — — ECON1 TXRST RXRST DMAST WDTCON — ...
Page 87
... TABLE 5-5: REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 T3CON RD16 T3CCP2 T3CKPS1 (5) PSPCON IBF OBF IBOV SPBRG1 EUSART1 Baud Rate Generator Register Low Byte RCREG1 EUSART1 Receive Register TXREG1 EUSART1 Transmit Register TXSTA1 CSRC TX9 TXEN ...
Page 88
... PIC18F97J60 FAMILY TABLE 5-5: REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 PORTF RF7 RF6 RF5 (6) (6) PORTE RE7 RE6 RE5 (5) (5) PORTD RD7 RD6 RD5 PORTC RC7 RC6 RC5 PORTB RB7 RB6 RB5 (6) PORTA RJPU — RA5 ...
Page 89
... TABLE 5-5: REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 ESTAT — BUFER — EIE — PKTIE DMAIE EDMACSH DMA Checksum Register High Byte EDMACSL DMA Checksum Register Low Byte EDMADSTH — — — EDMADSTL DMA Destination Register Low Byte EDMANDH — ...
Page 90
... PIC18F97J60 FAMILY TABLE 5-5: REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 EHT7 Hash Table Register Byte 7 EHT6 Hash Table Register Byte 6 EHT5 Hash Table Register Byte 5 EHT4 Hash Table Register Byte 4 EHT3 Hash Table Register Byte 3 EHT2 ...
Page 91
... For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY register then reads back as ‘000u u1uu’ recom- mended, therefore, that only BCF, BSF, SWAPF, MOVFF ...
Page 92
... PIC18F97J60 FAMILY 5.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 5.6 “Data Memory and the Extended Instruction Set” for more information. While the program memory can be addressed in only one way – ...
Page 93
... FCCh will be added to that of the W register and stored back in FCCh. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L ...
Page 94
... PIC18F97J60 FAMILY 5.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “virtual” registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on its stored value ...
Page 95
... Address Pointer specified by FSR2. The offset and the contents of FSR2 are added to obtain the target address of the operation. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 5.6.2 INSTRUCTIONS AFFECTED BY INDEXED LITERAL OFFSET MODE Any of the core PIC18 instructions that can use Direct Addressing are potentially affected by the Indexed Literal Offset Addressing mode ...
Page 96
... PIC18F97J60 FAMILY FIGURE 5-10: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF (Opcode: 0010 01da ffff ffff) When and f ≥ 60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and FFFh ...
Page 97
... BSR. F60h FFFh © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use Direct Addressing as before. Any indirect or ...
Page 98
... PIC18F97J60 FAMILY NOTES: DS39762E-page 98 © 2009 Microchip Technology Inc. ...
Page 99
... Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
Page 100
... PIC18F97J60 FAMILY FIGURE 6-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash Program Memory”. ...
Page 101
... Initiates a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software Write cycle complete bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY R/W-0 R/W-x R/W-0 FREE WRERR WREN U = Unimplemented bit, read as ‘ ...
Page 102
... PIC18F97J60 FAMILY 6.2.2 TABLE LATCH REGISTER (TABLAT) The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TABLE POINTER REGISTER (TBLPTR) The Table Pointer (TBLPTR) register addresses a byte within the program memory ...
Page 103
... MOVFW TABLAT, W MOVF WORD_ODD © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
Page 104
... PIC18F97J60 FAMILY 6.4 Erasing Flash Program Memory The minimum erase block is 1024 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be Bulk Erased. Word Erase in the Flash array is not supported. When initiating an erase sequence from the micro- controller itself, a block of 1024 bytes of program memory is erased ...
Page 105
... See parameter D132B (V ) for specific limits. PEW Note 1: Unlike previous PIC MCU devices, members of the PIC18F97J60 family do not reset the holding registers after a write occurs. The holding registers must be cleared or overwritten before a programming sequence maintain the endurance of the program ...
Page 106
... PIC18F97J60 FAMILY EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_BLOCK BSF EECON1, WREN BSF EECON1, FREE BCF INTCON, GIE MOVLW 55h MOVWF EECON2 MOVLW 0AAh MOVWF EECON2 BSF EECON1, WR BSF ...
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... EECON1 — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 6.5.4 PROTECTION AGAINST SPURIOUS WRITES To protect against spurious writes to Flash program memory, the write initiate sequence must also be followed. See Section 24.0 “ ...
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... PIC18F97J60 FAMILY NOTES: DS39762E-page 108 © 2009 Microchip Technology Inc. ...
Page 109
... For the sake of clarity, only I/O port and external bus assignments are shown here. One or more additional multiplexed features may be available on some pins. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY The bus is implemented with 28 pins, multiplexed across four I/O ports. Three ports (PORTD, PORTE ...
Page 110
... PIC18F97J60 FAMILY 7.1 External Memory Bus Control The operation of the interface is controlled by the MEMCON register (Register 7-1). This register is available in all program memory operating modes except Microcontroller mode. In this mode, the register is disabled and cannot be written to. The EBDIS bit (MEMCON<7>) controls the operation of the bus and related port functions ...
Page 111
... Address and Data Width The PIC18F97J60 family of devices can be indepen- dently configured for different address and data widths on the same memory bus. Both address and data widths are set by Configuration bits in the CONFIG3L register. As Configuration bits, this means that these options can only be configured by programming the device and are not controllable in software ...
Page 112
... Program Memory Modes and the External Memory Bus The PIC18F97J60 family of devices is capable of operating in one of two program memory modes, using combinations of on-chip and external program memory. The functions of the multiplexed port pins depend on the program memory mode selected, as well as the setting of the EBDIS bit ...
Page 113
... BYTE WRITE MODE Figure 7-1 shows an example of 16-Bit Byte Write mode for PIC18F97J60 family devices. This mode is used for two separate 8-bit memories connected for 16-bit operation. This generally includes basic EPROM and Flash devices. It allows table writes to byte-wide external memories ...
Page 114
... WORD WRITE MODE Figure 7-2 shows an example of 16-Bit Word Write mode for PIC18F97J60 family devices. This mode is used for word-wide memories which include some of the EPROM and Flash type memories. This mode allows opcode fetches and table reads from all forms of 16-bit memory, and table writes to any type of word-wide external memories ...
Page 115
... Upper order address lines are used only for 20-bit address width. 3: Demultiplexing is only required when multiple memory devices are accessed. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC standard Flash memories require that a controller I/O port pin be connected to the memory’ ...
Page 116
... PIC18F97J60 FAMILY 7.6.4 16-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 7-4 and Figure 7-5. FIGURE 7-4: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) ...
Page 117
... This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY will enable one byte of program memory for a portion of the instruction cycle, then BA0 will change and the second byte will be enabled to form the 16-bit instruc- tion word ...
Page 118
... PIC18F97J60 FAMILY 7.7.1 8-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 7-7 and Figure 7-8. FIGURE 7-7: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) ...
Page 119
... Microchip Technology Inc. PIC18F97J60 FAMILY In Sleep and Idle modes, the microcontroller core does not need to access data; bus operations are suspended. The state of the external bus is frozen, with ...
Page 120
... PIC18F97J60 FAMILY NOTES: DS39762E-page 120 © 2009 Microchip Technology Inc. ...
Page 121
... Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY EXAMPLE 8- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL EXAMPLE 8-2: ...
Page 122
... PIC18F97J60 FAMILY Example 8-3 shows the sequence unsigned multiplication. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 8- UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L • ARG2H:ARG2L RES3:RES0 = 16 (ARG1H • ARG2H • (ARG1H • ARG2L • (ARG1L • ARG2H • 2 (ARG1L • ...
Page 123
... INTERRUPTS Members of the PIC18F97J60 family of devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 0008h and the low-priority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress ...
Page 124
... PIC18F97J60 FAMILY FIGURE 9-1: PIC18F97J60 FAMILY INTERRUPT LOGIC PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:5,3,1:0> PIE2<7:5,3,1:0> IPR2<7:5,3,1:0> PIR3<7:0> PIE3<7:0> IPR3<7:0> High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:5,3,1:0> PIE2<7:5,3,1:0> IPR2<7:5,3,1:0> PIR3<7:0> PIE3<7:0> IPR3<7:0> DS39762E-page 124 TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF ...
Page 125
... Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit ...
Page 126
... PIC18F97J60 FAMILY REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values ...
Page 127
... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY R/W-0 R/W-0 R/W-0 ...
Page 128
... PIC18F97J60 FAMILY 9.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 ...
Page 129
... No TMR1/TMR3 register capture occurred Compare mode TMR1/TMR3 register compare match occurred (must be cleared in software TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY R/W-0 R/W-0 U-0 r BCL1IF — Unimplemented bit, read as ‘0’ ...
Page 130
... PIC18F97J60 FAMILY REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R/W-0 R-0 (1) (1) SSP2IF BCL2IF RC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 SSP2IF: MSSP2 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) ...
Page 131
... TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled Note 1: Implemented in 100-pin devices in Microcontroller mode only. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY R/W-0 R/W-0 R/W-0 TX1IE SSP1IE CCP1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) ...
Page 132
... PIC18F97J60 FAMILY REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 R/W-0 OSCFIE CMIE ETHIE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit ...
Page 133
... Disabled bit 0 CCP3IE: ECCP3 Interrupt Enable bit 1 = Enabled 0 = Disabled Note 1: Implemented in 100-pin devices only. 2: Implemented in 80-pin and 100-pin devices only. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY R-0 R/W-0 R/W-0 (2) (2) TX2IE TMR4IE CCP5IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 134
... PIC18F97J60 FAMILY 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...
Page 135
... TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY R/W-1 R/W-1 U-0 r BCL1IP — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 136
... PIC18F97J60 FAMILY REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W-1 R/W-1 (1) (1) SSP2IP BCL2IP RC2IP bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 SSP2IP: MSSP2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 module) ...
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... For details of bit operation, see Register 4-1. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register 4-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-1. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY R/W-1 R-1 R Unimplemented bit, read as ‘0’ ...
Page 138
... PIC18F97J60 FAMILY 9.6 INTx Pin Interrupts External interrupts on the RB0/INT0/FLT0, RB1/INT1, RB2/INT2 and RB3/INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxIF, is set ...
Page 139
... RD TRIS PORT © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 10.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V 10 ...
Page 140
... PIC18F97J60 FAMILY 10.1.2 INPUT PINS AND VOLTAGE CONSIDERATIONS The voltage tolerance of pins used as device inputs is dependent on the pin’s input function. Pins that are used as digital only inputs are able to handle DC voltages up to 5.5V, a level typical for digital logic circuits. In contrast, ...
Page 141
... ADCON1 — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: Implemented in 80-pin and 100-pin devices only. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY I/O I/O Type O DIG LATA<0> data output; not affected by analog input. I TTL PORTA< ...
Page 142
... PIC18F97J60 FAMILY 10.3 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port fully implemented on all devices. The corresponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i ...
Page 143
... Note 1: Alternate assignment for ECCP2/P2A when the CCP2MX Configuration bit is cleared (100-pin devices in Extended Microcontroller mode). Default assignment is RC1. 2: All other pin functions are disabled when ICSP or ICD is enabled. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY I/O I/O Type O DIG LATB<0> data output. ...
Page 144
... PIC18F97J60 FAMILY TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit 7 Bit 6 PORTB RB7 RB6 LATB LATB7 LATB6 TRISB TRISB7 TRISB6 INTCON GIE/GIEH PEIE/GIEL TMR0IE INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INTCON3 INT2IP INT1IP Legend: Shaded cells are not used by PORTB. ...
Page 145
... TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Note: These pins are configured as digital inputs on any device Reset. ...
Page 146
... PIC18F97J60 FAMILY TABLE 10-7: PORTC FUNCTIONS TRIS Pin Name Function I/O Setting RC0/T1OSO/ RC0 O 0 T13CKI I 1 T1OSO O x T13CKI I 1 RC1/T1OSI/ RC1 O 0 ECCP2/P2A I 1 T1OSI I x (1) ECCP2 (1) P2A O 0 RC2/ECCP1/ RC2 O 0 P1A I 1 ECCP1 P1A O 0 RC3/SCK1/ RC3 ...
Page 147
... TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 PORTC RC7 RC6 LATC LATC7 LATC6 TRISC TRISC7 TRISC6 © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 LATC5 LATC4 LATC3 LATC2 TRISC5 TRISC4 TRISC3 ...
Page 148
... PIC18F97J60 FAMILY 10.5 PORTD, TRISD and LATD Registers PORTD is implemented as a bidirectional port in two ways: • 64-pin and 80-pin devices: 3 bits (RD<2:0>) • 100-pin devices: 8 bits (RD<7:0>) The corresponding Data Direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode) ...
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... External memory interface I/O takes priority over all other digital and PSP I/O. 3: These features are implemented on this pin only on 64-pin devices; for all other devices, they are multiplexed with RE6/RH7 (P1B), RG0 (ECCP3/P3A) or RG3 (CCP4/P3D). © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY I/O I/O Type O DIG LATD< ...
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... PIC18F97J60 FAMILY TABLE 10-9: PORTD FUNCTIONS (CONTINUED) TRIS Pin Name Function Setting (1) RD5/AD5/ RD5 0 PSP5/SDI2/ 1 (1) SDA2 (1) AD5 x x (1) PSP5 x x (1) SDI2 1 (1) SDA2 1 1 (1) RD6/AD6/ RD6 0 PSP6/SCK2/ 1 (1) SCL2 (1) AD6 x x (1) PSP6 x x (1) SCK2 0 1 (1) SCL2 0 1 (1) RD7/AD7/ RD7 0 (1) ...
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... The pull-ups are disabled on all device Resets. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY PORTE is also multiplexed with Enhanced PWM outputs B and C for ECCP1 and ECCP3 and outputs B, C and D for ECCP2. For 80-pin and 100-pin devices, their default assignments are on PORTE< ...
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... PIC18F97J60 FAMILY TABLE 10-11: PORTE FUNCTIONS TRIS Pin Name Function Setting RE0/AD8/RD/ RE0 0 P2D 1 (1) AD8 P2D 0 RE1/AD9/WR/ RE1 0 P2C 1 (1) AD9 P2C 0 RE2/AD10/CS/ RE2 0 P2B 1 (1) AD10 P2B 0 RE3/AD11/ RE3 0 P3C 1 (1) AD11 x x (3) P3C 0 RE4/AD12/ RE4 ...
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... TRISE7 TRISE6 LATA RDPU REPU Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE. Note 1: Unimplemented on 64-pin devices; read as ‘0’. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY I/O I/O Type O DIG LATE<5> data output PORTE<5> data input; weak pull-up when REPU bit is set. ...
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... PIC18F97J60 FAMILY 10.7 PORTF, LATF and TRISF Registers PORTF is implemented as a bidirectional port in two different ways: • 64-pin and 80-pin devices: 7 bits wide (RF<7:1>) • 100-pin devices: 8 bits wide (RF<7:0>) The corresponding Data Direction register is TRISF. Setting a TRISF bit (= 1) will make the corresponding PORTF pin an input (i ...
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... CVREN CVROE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF. Note 1: Implemented on 100-pin devices only. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY I/O Type DIG LATF<0> data output; not affected by analog input. ST PORTF<0> data input; disabled when analog input enabled. ...
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... PIC18F97J60 FAMILY 10.8 PORTG, TRISG and LATG Registers Depending on the particular device, PORTG is implemented as a bidirectional port in one of three ways: • 64-pin devices: 1 bit wide (RG<4>) • 80-pin devices: 5 bits wide (RG<4:0>) • 100-pin devices: 8 bits wide (RG<7:0>) The corresponding Data Direction register is TRISG. ...
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... O = Output Input, DIG = Digital Output Schmitt Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Implemented on 80-pin and 100-pin devices only. 2: Implemented on 100-pin devices only. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY I/O Type DIG LATG<0> data output PORTG< ...
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... PIC18F97J60 FAMILY TABLE 10-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG Name Bit 7 Bit 6 (1) (1) PORTG RG7 RG6 RG5 (1) (1) LATG LATG7 LATG6 LATG5 (1) (1) TRISG TRISG7 TRISG6 TRISG5 Note 1: Implemented on 100-pin devices only. 2: Implemented on 80-pin and 100-pin devices only. DS39762E-page 158 Bit 5 ...
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... All pins on PORTH are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY When the external memory interface is enabled, four of the PORTH pins function as the high-order address lines for the interface. The address output from the interface takes priority over other digital I/O ...
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... PIC18F97J60 FAMILY TABLE 10-17: PORTH FUNCTIONS TRIS Pin Name Function I/O Setting RH0/A16 RH0 (1) A16 O x RH1/A17 RH1 (1) A17 O x RH2/A18 RH2 (1) A18 O x RH3/A19 RH3 (1) A19 x O RH4/AN12/P3C RH4 AN12 I (2) P3C O 0 RH5/AN13/P3B RH5 AN13 I (2) P3B O 0 RH6/AN14/P1C ...
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... Note: These pins are configured as digital inputs on any device Reset. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY When the external memory interface is enabled, all of the PORTJ pins function as control outputs for the interface. This occurs automatically when the interface is enabled by clearing the EBDIS control bit (MEMCON< ...
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... PIC18F97J60 FAMILY TABLE 10-19: PORTJ FUNCTIONS TRIS Pin Name Function Setting (1) (1) RJ0/ALE RJ0 0 1 (1) ALE x (1) (1) RJ1/OE RJ1 (1) (1) RJ2/WRL RJ2 0 1 (1) WRL x (1) (1) RJ3/WRH RJ3 0 1 (1) WRH x RJ4/BA0 RJ4 0 1 (2) BA0 x RJ5/CE RJ5 (1) (1) RJ6/LB RJ6 0 1 (1) ...
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... OBF bits can be polled and the appropriate action taken. The timing for the control signals in Write and Read modes is shown in Figure 10-3 and Figure 10-4, respectively. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY FIGURE 10-2: PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) Data Bus ...
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... PIC18F97J60 FAMILY REGISTER 10-1: PSPCON: PARALLEL SLAVE PORT CONTROL REGISTER R-0 R-0 R/W-0 IBF OBF IBOV bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IBF: Input Buffer Full Status bit word has been received and is waiting to be read by the CPU ...
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... PSPIF ADIF RC1IF PIE1 PSPIE ADIE RC1IE IPR1 PSPIP ADIP RC1IP Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RD5 RD4 RD3 LATD4 ...
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... PIC18F97J60 FAMILY NOTES: DS39762E-page 166 © 2009 Microchip Technology Inc. ...
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... Prescale value 000 = 1:2 Prescale value © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 11-1 ...
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... PIC18F97J60 FAMILY 11.1 Timer0 Operation Timer0 can operate as either a timer or a counter; the mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 11.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles ...
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... T08BIT TRISA — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 11.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution ...
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... PIC18F97J60 FAMILY NOTES: DS39762E-page 170 © 2009 Microchip Technology Inc. ...
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... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY A simplified block diagram of the Timer1 module is shown in Figure 12-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 12-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
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... PIC18F97J60 FAMILY 12.1 Timer1 Operation Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 12-1: TIMER1 BLOCK DIAGRAM ...
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... PIC18F97J60 27 pF T1OSI XTAL 32.768 kHz T1OSO Note: See the Notes with Table 12-1 for additional information about capacitor selection. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 12-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Oscillator Freq. C1 Type ( kHz 27 pF Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
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... PIC18F97J60 FAMILY If a high-speed circuit must be located near the oscilla- tor (such as the ECCP1 pin in Output Compare or PWM mode, or the primary oscillator using the OSC2 pin), a grounded guard ring around the oscillator circuit, as shown in Figure 12-4, may be helpful when used on a single-sided PCB or in addition to a ground plane. ...
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... T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: Shaded cells are not used by the Timer1 module. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ; Initialize timekeeping registers ...
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... PIC18F97J60 FAMILY NOTES: DS39762E-page 176 © 2009 Microchip Technology Inc. ...
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... Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 13.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by-16 prescale options ...
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... PIC18F97J60 FAMILY 13.2 Timer2 Interrupt Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) pro- vides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1< ...
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... TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY A simplified block diagram of the Timer3 module is shown in Figure 14-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 14-2. The Timer3 module is controlled through the T3CON register (Register 14-1). It also selects the clock source options for the CCPx and ECCPx modules ...
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... PIC18F97J60 FAMILY 14.1 Timer3 Operation Timer3 can operate in one of three modes: • Timer • Synchronous Counter • Asynchronous Counter FIGURE 14-1: TIMER3 BLOCK DIAGRAM Timer1 Oscillator T1OSO/T13CKI T1OSI (1) T1OSCEN T3CKPS1:T3CKPS0 T3SYNC TMR3ON ECCPx Special Event Trigger ECCPx Select from T3CON<6,3> Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. ...
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... T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’ reserved. Shaded cells are not used by the Timer3 module. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 14.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
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... PIC18F97J60 FAMILY NOTES: DS39762E-page 182 © 2009 Microchip Technology Inc. ...
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... T4CKPS1:T4CKPS0: Timer4 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 15.1 Timer4 Operation Timer4 can be used as the PWM time base for the PWM mode of the CCP module. The TMR4 register is readable and writable and is cleared on any device Reset ...
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... PIC18F97J60 FAMILY 15.2 Timer4 Interrupt The Timer4 module has an 8-Bit Period register, PR4, which is both readable and writable. Timer4 increments from 00h until it matches PR4 and then resets to 00h on the next increment cycle. The PR4 register is initialized to FFh upon Reset. FIGURE 15-1: ...
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... CAPTURE/COMPARE/PWM (CCP) MODULES Members of the PIC18F97J60 family of devices all have a total of five CCP (Capture/Compare/PWM) modules. Two of these (CCP4 and CCP5) implement standard Capture, Compare and Pulse-Width Modulation (PWM) modes and are discussed in this section. The other three modules (ECCP1, ECCP2, ...
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... PIC18F97J60 FAMILY 16.1 CCPx Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. ...
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... Q1:Q4 CCP5CON<3:0> CCP5 Pin Prescaler ÷ © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 16.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode ...
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... PIC18F97J60 FAMILY 16.3 Compare Mode In Compare mode, the 16-bit CCPRx register value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the CCPx pin: • can be driven high • can be driven low • can be toggled (high-to-low or low-to-high) • ...
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... Legend: — = unimplemented, read as ‘0’ reserved. Shaded cells are not used by Capture/Compare, Timer1 or Timer3. Note 1: This bit is only available in 80-pin and 100-pin devices; otherwise unimplemented and reads as ‘0’. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 ...
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... PIC18F97J60 FAMILY 16.4 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCPx pin produces 10-bit resolution PWM output. Since the CCP4 and CCP5 pins are multiplexed with a PORTG data latch, the appropriate TRISG bit must be cleared to make the CCP4 or CCP5 pin an output. ...
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... Timer Prescaler (1, 4, 16) PR2 Value FFh Maximum Resolution (bits) © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 16.4.3 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCPx module for PWM operation: 1. Set the PWM period by writing to the PR2 (PR4) register ...
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... PIC18F97J60 FAMILY TABLE 16-4: REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4 Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL RCON IPEN — PIR1 PSPIF ADIF PIE1 PSPIE ADIE IPR1 PSPIP ADIP PIR3 SSP2IF BCL2IF PIE3 SSP2IE BCL2IE IPR3 SSP2IP BCL2IP TRISG TRISG7 TRISG6 ...
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... ENHANCED CAPTURE/ COMPARE/PWM (ECCP) MODULES In the PIC18F97J60 family of devices, three of the CCP modules are implemented as standard CCP modules with Enhanced PWM capabilities. These include the provision for output channels, user-selectable polarity, dead-band control and automatic shutdown and restart. The Enhanced features are discussed in detail in Section 17.4 “ ...
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... PIC18F97J60 FAMILY 17.1 ECCPx Outputs and Configuration Each of the Enhanced CCPx modules may have up to four PWM outputs, depending on the selected operating mode. These outputs, designated PxA through PxD, are multiplexed with various I/O pins. Some ECCPx pin assignments are constant, while others change based on device configuration ...
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... Compatible CCP ECCP2 00xx 11xx Dual PWM 10xx 11xx Quad PWM x1xx 11xx Legend Don’t care. Shaded cells indicate pin assignments not used by ECCP2 in a given mode. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY RD0 or RC2 RE5 (1) RE6 ECCP1 RD0/RE6 RE5 ...
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... PIC18F97J60 FAMILY TABLE 17-3: PIN CONFIGURATIONS FOR ECCP3 CCP3CON RD1 or ECCP Mode Configuration RG0 64-Pin Devices; 80-Pin Devices, ECCPMX = 1; 100-Pin Devices, ECCPMX = 1, Microcontroller mode: Compatible CCP ECCP3 00xx 11xx Dual PWM 10xx 11xx Quad PWM x1xx 11xx 100-Pin Devices, ECCPMX = 0, All Program Memory modes: ...
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... Note: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Enhanced PWM waveforms do not exactly match the standard PWM waveforms, but are instead, offset by ...
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... PIC18F97J60 FAMILY 17.4.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> bits contain the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is ...
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... Duty Cycle = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (ECCP1DEL<6:0>) OSC Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 17.4.6 “Programmable Dead-Band Delay”). © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 0 Duty Cycle Period (1) (1) Delay Delay 0 Duty ...
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... PIC18F97J60 FAMILY 17.4.4 HALF-BRIDGE MODE In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the P1A pin, while the complemen- tary PWM output signal is output on the P1B pin (Figure 17-4). This mode can be used for half-bridge ...