PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet
PIC18F97J60-I/PF
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PIC18F97J60-I/PF Summary of contents
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... PIC18F97J60 family in all package types. 2.1 Pin Diagrams The pin diagrams for the PIC18F97J60 family are shown in Figure 2-1 through Figure 2-3. The pins that are required for programming are listed in Table 2-1 and shown in darker lettering in the figures. ...
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... PIC18F97J60 FAMILY FIGURE 2-1: PIC18F97J60 FAMILY PIN DIAGRAMS 64-Pin TQFP RE1 1 RE0 2 RB0 3 RB1 4 RB2 5 RB3 6 MCLR 7 RG4 DDCORE CAP 10 RF7 11 RF6 12 RF5 13 RF4 14 RF3 15 RF2 16 Note: Bold-faced names indicate the pins that are required for programming. For more information, see Table 2-1. ...
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... FIGURE 2-2: PIC18F97J60 FAMILY PIN DIAGRAMS (CONTINUED) 80-Pin TQFP 80 79 RH2 1 RH3 2 RE1 3 RE0 4 RB0 5 RB1 6 RB2 7 RB3 8 MCLR 9 RG4 DDCORE CAP 12 RF7 13 RF6 14 RF5 15 RF4 16 RF3 17 RF2 18 RH7 19 RH6 Note: Bold-faced names indicate the pins that are required for programming. For more information, see Table 2-1. ...
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... PIC18F97J60 FAMILY FIGURE 2-3: PIC18F97J60 FAMILY PIN DIAGRAMS (CONTINUED) 100-Pin TQFP 1 RH2 2 RH3 RE1 3 RE0 4 RB0 5 RB1 6 RB2 7 RB3 RG6 10 RG5 11 RF0 12 MCLR 13 RG4 DDCORE CAP RF7 18 RF6 19 RF5 20 RF4 21 RF3 22 RF2 23 RH7 24 RH6 25 Note: Bold-faced names indicate the pins that are required for programming. For more information, see Table 2-1. ...
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... V DDCORE V SS 2.2 Memory Maps PIC18F97J60 family devices are available in three program memory sizes: 64 Kbytes, 96 Kbytes and 128 Kbytes. The overall memory maps for all devices are shown in Figure 2-5. © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY For purposes of code protection, the program memory for every device is treated as a single block ...
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... PIC18F97J60 FAMILY FIGURE 2-5: MEMORY MAPS FOR PIC18F97J60 FAMILY DEVICES PIC18FX6J60 (64 Kbytes) Code Memory Flash Configuration Words Unimplemented Read as ‘0’ Configuration Space Configuration Words Configuration Space Device IDs Memory spaces are unimplemented or unavailable in normal execution mode and read as ‘0’. ...
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... Microchip Technology Inc. PIC18F97J60 FAMILY 2.4 Entering and Exiting ICSP Program/Verify Mode Entry into ICSP modes for PIC18F97J60 family devices is somewhat different than previous PIC18 devices. As shown in Figure 2-7, entering ICSP Program/Verify mode requires three steps: 1. Voltage is briefly applied to the MCLR pin. ...
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... PIC18F97J60 FAMILY FIGURE 2-8: EXITING PROGRAM/ VERIFY MODE P16 V MCLR PGD PGC PGD = Input 2.5 Serial Program/Verify Operation The PGC pin is used as a clock input pin and the PGD pin is used for entering command bits and data input/ output during serial operation. Commands and data are ...
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... WR bit. 3.1 ICSP Erase 3.1.1 ICSP BULK ERASE Devices of the PIC18F97J60 family may be Bulk Erased by writing 0180h to the table address 3C0005h:3C0004h. The basic sequence is shown in Figure 3-1 and demonstrated in Table 3-1. Since the code-protect Configuration bit is stored in the ...
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... WR bit in EECON1 is set, a NOP is issued, where the 4th PGC is held high for the duration of the Row Erase time, P10. The code sequence to Row Erase a PIC18F97J60 fam- ily device is shown in Table 3-2. The flowchart shown in Figure 3-3 depicts the logic necessary to completely erase a PIC18F97J60 family device. The timing diagram that details the “ ...
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... Programming code memory is accomplished by first loading data into the write buffer and then initiating a programming sequence. The write buffer for all devices in the PIC18F97J60 family is 64 bytes; it can be mapped to any integral boundary of 64 bytes, beginning at 000000h. The actual memory write sequence takes the contents of this buffer and programs the 64 bytes of code memory that contains the Table Pointer ...
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... PIC18F97J60 FAMILY FIGURE 3-5: PROGRAM CODE MEMORY FLOW LoopCount = LoopCount + 1 FIGURE 3-6: TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (1111 PGC P5 PGD 4-Bit Command DS39688D-page 12 Start LoopCount = 0 Configure Device for Writes Load 2 Bytes to Write Buffer at <Addr> All No Bytes Written? Yes Start Write Sequence ...
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... Step 6: To continue modifying data, repeat Steps 1 through 4, where the Address Pointer is incremented by 1024 bytes at each iteration of the loop. Step 7: Disable writes. 0000 94 A6 © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 3.2.2 CONFIGURATION WORD PROGRAMMING Since the Flash Configuration Words are stored in program memory, they are programmed as if they were program data. Refer to Section 3.2 “ ...
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... PIC18F97J60 FAMILY 4.0 READING THE DEVICE 4.1 Read Code Memory Code memory is accessed one byte at a time via the 4-bit command, ‘1001’ (table read, post-increment). The contents of memory pointed to by the Table Pointer (TBLPTRU:TBLPTRH:TBLPTRL) are serially output on PGD. The 4-bit command is shifted in LSb first. The read is executed during the next 8 clocks, then shifted out on PGD during the last 8 clocks, LSb to MSb ...
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... No Code Memory Verified? Yes Done © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY 4.3 Blank Check The term “Blank Check” means to verify that the device has no programmed memory cells. All memories must be verified: code memory and Configuration bits. The Device ID registers (3FFFFEh:3FFFFFh) should be ignored. A “ ...
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... PIC18F97J60 FAMILY 5.0 CONFIGURATION WORD The Configuration Words of the PIC18F97J60 family devices are implemented as volatile memory registers, as opposed to the programmable nonvolatile memory used in other PIC18 devices. All of the Configuration registers (CONFIG1L, CONFIG1H, CONFIG2H, CONFIG3L and CONFIG3H) automatically loaded following each device Reset. ...
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... TABLE 5-3: PIC18F97J60 FAMILY BIT DESCRIPTIONS Configuration Bit Name Words DEBUG CONFIG1L XINST CONFIG1L STVREN CONFIG1L WDTEN CONFIG1L CP0 CONFIG1H IESO CONFIG2L FCMEN CONFIG2L FOSC2 CONFIG2L FOSC1:FOSC0 CONFIG2L © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Description Background Debugger Enable bit 1 = Background debugger disabled, RB6 and RB7 configured as general ...
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... PIC18F97J60 FAMILY TABLE 5-3: PIC18F97J60 FAMILY BIT DESCRIPTIONS (CONTINUED) Configuration Bit Name Words WDTPS3:WDTPS0 CONFIG2H WAIT CONFIG3L BW CONFIG3L EMB1:EMB0 CONFIG3L EASHFT CONFIG3L ETHLED CONFIG3H ECCPMX CONFIG3H CCP2MX CONFIG3H DS39688D-page 18 Description Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 ...
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... Code Protection has been enabled. The process for reading the device IDs is shown in Figure 5-1. A complete list of device ID values for the PIC18F97J60 family is presented in Table 5-4. TABLE 5-4: DEVICE ID VALUES Device ...
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... PIC18F97J60 FAMILY 5.2 Checksum Computation The checksum is calculated by summing the contents of all code memory locations and the device Configura- tion Words, appropriately masked. Significant 16 bits of this sum are the checksum. The checksum calculation differs depending on whether or not code protection is enabled. Since the ...
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... Note 1: V must be supplied to the V DDCORE Section 2.1.1 “On-Chip Voltage Regulator” for more information must also be supplied to the AV DD regulator is used. AV and AV DD © 2009 Microchip Technology Inc. PIC18F97J60 FAMILY Min Max 2.35 2.70 ENVREG = V V 3.60 SS DDCORE ENVREG = V 2.65 3.60 DD — ...
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... PIC18F97J60 FAMILY TABLE 6-1: TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE (CONTINUED) Standard Operating Conditions Operating Temperature: 25°C is recommended Param Sym Characteristic No Serial Clock (PGC) Period PGC P2A T Serial Clock (PGC) Low Time PGCL P2B T Serial Clock (PGC) High Time PGCH Input Data Setup Time to Serial Clock ↓ ...
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... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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