PIC18F96J65-I/PT Microchip Technology, PIC18F96J65-I/PT Datasheet - Page 7

• Manufacturer Part Number: PIC18F96J65-I/PT
• Description: IC PIC MCU FLASH 48KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F96J65-I/PT

• Core Size: 8-Bit
• Program Memory Size: 96KB (48K x 16)
• Core Processor: PIC
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: FLASH
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 70
• Ram Memory Size: 3.71875KB
• Cpu Speed: 41.667MHz
• No. Of Timers: 5
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2.3
Figure 2-6 shows the high-level overview of the
programming process. First, a Bulk Erase is performed.
Next, the code memory is programmed. Since the only
nonvolatile Configuration Words are within the code
memory space, they too are programmed as if they
were code. Code memory (including the Configuration
Words) is then verified to ensure that programming was
successful.
FIGURE 2-6:
FIGURE 2-7:
© 2009 Microchip Technology Inc.
MCLR
V
PGD
PGC
DD
Overview of the Programming
Process
Program Memory
Verify Program
Enter ICSP™
Perform Bulk
P13
HIGH-LEVEL
PROGRAMMING FLOW
ENTERING PROGRAM/VERIFY MODE
Exit ICSP
Erase
Done
Done
Start
P19
V
b31
IH
0
b30
1
Program/Verify Entry Code = 4D434850h
b29
0
b28
P2B
0
P2A
PIC18F97J60 FAMILY
b27
2.4
Entry into ICSP modes for PIC18F97J60 family devices
is somewhat different than previous PIC18 devices. As
shown in Figure 2-7, entering ICSP Program/Verify
mode requires three steps:
1.
2.
3.
The programming voltage applied to MCLR is V
usually, V
holding at V
least P19 must elapse before presenting the key
sequence on PGD.
The key sequence is a specific 32-bit pattern,
‘0100 1101 0100 0011 0100 1000 0101 0000’
(more easily remembered as 4D434850h in hexa-
decimal). The device will enter Program/Verify mode
only if the sequence is valid. The Most Significant bit of
the most significant nibble must be shifted in first.
Once the key sequence is complete, V
applied to MCLR and held at that level for as long as
Program/Verify mode is to be maintained. An interval of
at least time P20 and P12 must elapse before present-
ing data on PGD. Signals appearing on PGD before
P12 has elapsed may not be interpreted as valid.
On successful entry, the program memory can be
accessed and programmed in serial fashion. While in
the Program/Verify mode, all unused I/Os are placed in
the high-impedance state.
Exiting Program/Verify mode is done by removing V
from MCLR, as shown in Figure 2-8. The only require-
ment for exit is that an interval, P16, should elapse
between the last clock and program signals on PGC
and PGD before removing V
When V
the ordinary operational mode and begin executing the
application instructions.
1
Voltage is briefly applied to the MCLR pin.
A 32-bit key sequence is presented on PGD.
Voltage is reapplied to MCLR and held.
...
IH
Entering and Exiting ICSP
Program/Verify Mode
DD
is reapplied to MCLR, the device will enter
b3
0
. There is no minimum time requirement for
IH
. After V
b2
0
b1
IH
0
V
is removed, an interval of at
IH
b0
IH
0
.
P20
DS39688D-page 7
P12
IH
must be
IH
, or
IH