PIC18F96J65-I/PT Microchip Technology, PIC18F96J65-I/PT Datasheet - Page 22

• Manufacturer Part Number: PIC18F96J65-I/PT
• Description: IC PIC MCU FLASH 48KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F96J65-I/PT

• Core Size: 8-Bit
• Program Memory Size: 96KB (48K x 16)
• Core Processor: PIC
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: FLASH
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 70
• Ram Memory Size: 3.71875KB
• Cpu Speed: 41.667MHz
• No. Of Timers: 5
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F97J60 FAMILY
TABLE 6-1:
DS39688D-page 22
Standard Operating Conditions
Operating Temperature: 25°C is recommended
P2
P2A
P2B
P3
P4
P5
P5A
P6
P9
P10
P11
P12
P13
P14
P16
P19
P20
Note 1:
Param
No.
2:
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
DLY
PGC
PGCL
PGCH
SET
HLD
DLY
DLY
DLY
DLY
DLY
HLD
SET
VALID
DLY
KEY
KEY
Sym
V
Section 2.1.1 “On-Chip Voltage Regulator” for more information.
V
regulator is used. AV
DDCORE
DD
1
1
1
1
2
5
6
7
2
2
8
1
2
A
must also be supplied to the AV
TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE (CONTINUED)
Serial Clock (PGC) Period
Serial Clock (PGC) Low Time
Serial Clock (PGC) High Time
Input Data Setup Time to Serial Clock ↓
Input Data Hold Time from PGC ↓
Delay between 4-bit Command and
Command Operand
Delay between 4-bit Command Operand
and Next 4-bit Command
Delay between Last PGC ↓ of Command
Byte to First PGC ↑ of Read of Data Word
Delay to allow Block Programming to
Occur
Delay to allow Row Erase to Occur
Delay to allow Bulk Erase to Occur
Input Data Hold Time from MCLR ↑
V
Data Out Valid from PGC ↑
Delay between Last PGC ↓ and MCLR ↓
Delay from First MCLR ↓ to First PGC ↑ for
Key Sequence on PGD
Delay from Last PGC ↓ for Key Sequence
on PGD to Second MCLR ↑
DD
must be supplied to the V
↑ Setup Time to MCLR ↑
DD
Characteristic
and AV
SS
should always be within ±0.3V of V
DDCORE
DD
pins during programming and to the ENVREG if the on-chip voltage
/V
CAP
pin if the on-chip voltage regulator is disabled. See
Min
100
475
400
100
3.4
40
40
15
15
40
40
20
49
10
20
40
1
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DD
and V
Units
ms
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
ns
ns
SS
© 2009 Microchip Technology Inc.
, respectively.
Conditions