ATMEGA32A-AU Atmel, ATMEGA32A-AU Datasheet - Page 87

• Manufacturer Part Number: ATMEGA32A-AU
• Description: MCU AVR 32K FLASH 16MHZ 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32A-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: 2-Wire/SPI/USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Data Rom Size: 1024 B
• Height: 1 mm
• Length: 10 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 10 mm
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.9.4
14.9.5
8155C–AVR–02/11
TIMSK – Timer/Counter Interrupt Mask Register
TIFR – Timer/Counter Interrupt Flag Register
The Output Compare Register contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an output compare interrupt, or to
generate a waveform output on the OC0 pin.
• Bit 1 – OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable
When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is executed if
a compare match in Timer/Counter0 occurs, that is, when the OCF0 bit is set in the Timer/Coun-
ter Interrupt Flag Register – TIFR.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, that is, when the TOV0 bit is set in the Timer/Counter Inter-
rupt Flag Register – TIFR.
• Bit 1 – OCF0: Output Compare Flag 0
The OCF0 bit is set (one) when a compare match occurs between the Timer/Counter0 and the
data in OCR0 – Output Compare Register0. OCF0 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, OCF0 is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE0 (Timer/Counter0 Compare Match Interrupt Enable), and
OCF0 are set (one), the Timer/Counter0 Compare Match Interrupt is executed.
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hard-
ware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared
by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Inter-
rupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In
phase correct PWM mode, this bit is set when Timer/Counter0 changes counting direction at
$00.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
OCIE2
OCF2
R/W
R/W
7
0
7
0
TOIE2
TOV2
R/W
R/W
6
0
6
0
TICIE1
R/W
ICF1
R/W
5
0
5
0
OCIE1A
OCF1A
R/W
R/W
4
0
4
0
OCIE1B
OCF1B
R/W
R/W
3
0
3
0
TOIE1
TOV1
R/W
R/W
2
0
2
0
OCIE0
OCF0
R/W
R/W
1
0
1
0
ATmega32A
TOIE0
TOV0
R/W
R/W
0
0
0
0
TIMSK
TIFR
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