ATMEGA32A-AU Atmel, ATMEGA32A-AU Datasheet - Page 302

• Manufacturer Part Number: ATMEGA32A-AU
• Description: MCU AVR 32K FLASH 16MHZ 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32A-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: 2-Wire/SPI/USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Data Rom Size: 1024 B
• Height: 1 mm
• Length: 10 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 10 mm
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 27-2.
Notes:
27.7
8155C–AVR–02/11
Symbol
t
t
SU;STO
BUF
1. In ATmega32A, this parameter is characterized and not 100% tested.
2. Required only for f
3. C
4. f
5. This requirement applies to all ATmega32A Two-wire Serial Interface operation. Other devices connected to the Two-wire
SPI Timing Characteristics
Serial Bus need only obey the general f
Parameter
Setup time for STOP condition
Bus free time between a STOP and START
condition
CK
b
= capacitance of one bus line in pF.
= CPU clock frequency
Two-wire Serial Bus Requirements (Continued)
Figure 27-5. Two-wire Serial Bus Timing
See
Table 27-3.
SCL
10
11
12
1
2
3
4
5
6
7
8
9
Figure 27-6
> 100kHz.
SCL
SDA
t
SU;STA
SCK to out high
SCK high/low
Rise/Fall time
SCK high/low
Rise/Fall time
SS low to out
SPI Timing Parameters
Description
SCK period
Out to SCK
SCK period
SCK to out
and
Setup
Hold
SCL
Figure 27-7
requirement.
t
HD;STA
t
t
of
LOW
for details.
f
f
f
f
SCL
SCL
SCL
SCL
Condition
Master
Master
Master
Master
Master
Master
Master
Master
Mode
Slave
Slave
Slave
Slave
t
HIGH
≤ 100kHz
> 100kHz
≤ 100kHz
> 100kHz
t
HD;DAT
t
LOW
4 • t
2 • t
Min
ck
ck
t
SU;DAT
See
50% duty cycle
Min
4.0
0.6
4.7
1.3
0.5 • t
Table 18-4
Typ
3.6
10
10
10
10
15
SCK
ATmega32A
t
SU;STO
t
Max
r
–
–
–
–
Max
1.6
t
BUF
Units
ns
µs
µs
µs
µs
µs
302