PIC24HJ16GP304-I/ML Microchip Technology, PIC24HJ16GP304-I/ML Datasheet - Page 40

• Manufacturer Part Number: PIC24HJ16GP304-I/ML
• Description: IC PIC MCU FLASH 16K 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ16GP304-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 16KB (5.5K x 24)
• Package / Case: 44-QFN
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 13x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24HJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24HJ32GP202/204 AND PIC24HJ16GP304
4.2.5
In addition to its use as a working register, the W15
register
PIC24HJ16GP304 devices is also used as a software
Stack Pointer. The Stack Pointer always points to the
first available free word and grows from lower to higher
addresses. It pre-decrements for stack pops and
post-increments for stack pushes, as shown in
Figure
the MSB of the PC is zero-extended before the push,
ensuring that the MSB is always clear.
The Stack Pointer Limit register (SPLIM) associated
with the Stack Pointer sets an upper address boundary
for the stack. SPLIM is uninitialized at Reset. Similarly,
the Stack Pointer, SPLIM<0> is forced to ‘0’ because all
stack operations must be word aligned.
When an EA is generated using W15 as a source or
destination pointer, the resulting address is compared
with the value in SPLIM. If the contents of the Stack
Pointer (W15) and the SPLIM register are equal and a
push operation is performed, a stack error trap will not
occur. The stack error trap will occur on a subsequent
push operation. For example, to cause a stack error
trap when the stack grows beyond address 0x1000 in
RAM, initialize the SPLIM with the value 0x0FFE.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be lesser than 0x0800. This prevents the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 4-4:
DS70289G-page 40
0x0000
Note:
4-4. For a PC push during any CALL instruction,
15
000000000
in
SOFTWARE STACK
A PC push during exception processing
concatenates the SRL register to the MSB
of the PC prior to the push.
<Free Word>
PC<15:0>
the
PC<22:16>
CALL STACK FRAME
PIC24HJ32GP202/204
0
POP : [--W15]
PUSH : [W15++]
W15 (before CALL)
W15 (after CALL)
and
4.2.6
The PIC24H product family supports Data RAM
protection features that enable segments of RAM to be
protected when used in conjunction with Boot and
Secure Code Segment Security. BSRAM (Secure RAM
segment for BS) is accessible only from the Boot
Segment Flash code when enabled. SSRAM (Secure
RAM segment for RAM) is accessible only from the
Secure Segment Flash code when enabled. See
Table 4-1
SFRs.
4.3
The addressing modes shown in
basis of the addressing modes optimized to support the
specific features of individual instructions. The
addressing modes provided in the MAC class of
instructions differ from those in the other instruction
types.
4.3.1
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first 8192
bytes of data memory (Near Data Space). Most file
register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
4.3.2
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 <function> Operand 2
where:
Operand 1 is always a working register (that is, the
addressing mode can only be register direct), which is
referred to as Wb.
Operand 2 can be a W register, fetched from data
memory, or a 5-bit literal. The result location can be
either a W register or a data memory location. The fol-
lowing addressing modes are supported by MCU
instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-Modified
• Register Indirect Pre-Modified
• 5-bit or 10-bit Literal
Note:
Instruction Addressing Modes
for an overview of the BSRAM and SSRAM
DATA RAM PROTECTION FEATURE
FILE REGISTER INSTRUCTIONS
MCU INSTRUCTIONS
Not all instructions support all the
addressing
Individual
different subsets of these addressing
modes.
© 2011 Microchip Technology Inc.
instructions
modes
Table 4-23
given
can
form the
support
above.