PIC24HJ16GP304-I/ML Microchip Technology, PIC24HJ16GP304-I/ML Datasheet
PIC24HJ16GP304-I/ML
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PIC24HJ16GP304-I/ML Summary of contents
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... PIC24HJ32GP202/204 and © 2011 Microchip Technology Inc. PIC24HJ16GP304 Data Sheet High-Performance, 16-bit Microcontrollers DS70289G ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Flash program memory ( Kbytes) • Data SRAM (2 Kbytes) • Boot and General Security for Program Flash © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 and PIC24HJ16GP304 Digital I/O: • Peripheral Pin Select Functionality • programmable digital I/O pins • Wake-up/Interrupt-on-Change for pins • ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 Communication Modules: • 4-wire SPI - Framing supports I/O interface to simple codecs - Supports 8-bit and 16-bit data - Supports all serial clock formats and sampling modes 2 • I C™ - Full Multi-Master Slave mode support - 7-bit and 10-bit addressing - Bus collision detection and arbitration ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 PIC24HJ32GP202/204 and PIC24HJ16GP304 Product Families The device names, pin counts, memory sizes and peripheral availability of each family are listed below, followed by their pinout diagrams. TABLE 1: PIC24HJ32GP202/204 AND PIC24HJ16GP304 CONTROLLER FAMILIES Device PIC24HJ32GP202 28 32 PIC24HJ32GP204 44 32 PIC24HJ16GP304 44 16 Note 1: Only two out of three timers are remappable ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 Pin Diagrams 28-Pin SDIP, SOIC, SSOP AN0/V AN1/V PGED1/AN2/C2IN-/RP0 PGEC1/AN3/C2IN+/RP1 AN4/RP2 AN5/RP3 OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 SOSCI/RP4 SOSCO/T1CK/CN0/RA4 PGED3/ASDA1/RP5 (2) 28-Pin QFN-S (1) PGED1/AN2/C2IN-/RP0 /CN4/RB0 (1) PGEC1/AN3/C2IN+/RP1 /CN5/RB1 (1) AN4/RP2 /CN6/RB2 (1) AN5/RP3 /CN7/RB3 OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 Note 1: The RPn pins can be used by any remappable peripheral. See ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 Pin Diagrams (Continued) (2) 44-Pin QFN (1) AN4/RP2 /CN6/RB2 (1) AN5/RP3 /CN7/RB3 (1) AN6/RP16 /CN8/RC0 (1) AN7/RP17 /CN9/RC1 (1) AN8/RP18 /CN10/RC2 OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 TDO/RA8 (1) SOSCI/RP4 /CN1/RB4 Note 1: The RPn pins can be used by any remappable peripheral. See 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 Pin Diagrams (Continued) 44-Pin TQFP (1) AN4/RP2 /CN6/RB2 (1) AN5/RP3 /CN7/RB3 (1) AN6/RP16 /CN8/RC0 (1) AN7/RP17 /CN9/RC1 (1) AN8/RP18 /CN10/RC2 OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 TDO/RA8 (1) SOSCI/RP4 /CN1/RB4 Note 1: The RPn pins can be used by any remappable peripheral. See 2: Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (V ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Guidelines for Getting Started with 16-bit Microcontrollers ........................................................................................................ 15 3.0 CPU............................................................................................................................................................................................ 19 4.0 Memory Organization ................................................................................................................................................................. 25 5.0 Flash Program Memory.............................................................................................................................................................. 47 6.0 Resets ....................................................................................................................................................................................... 53 7.0 Interrupt Controller ..................................................................................................................................................................... 61 8.0 Oscillator Configuration .............................................................................................................................................................. 89 9.0 Power-Saving Features.............................................................................................................................................................. 99 10.0 I/O Ports ................................................................................................................................................................................... 103 11.0 Timer1 ...................................................................................................................................................................................... 123 12 ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 NOTES: DS70289G-page 10 © 2011 Microchip Technology Inc. ...
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... PIC24HJ32GP202 • PIC24HJ32GP204 • PIC24HJ16GP304 Figure 1-1 shows a general block diagram of the core and peripheral modules in the PIC24HJ32GP202/204 and PIC24HJ16GP304 family of devices. lists the functions of the various pins shown in the pinout diagrams. © 2011 Microchip Technology Inc. and Reference in ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 FIGURE 1-1: PIC24HJ32GP202/204 AND PIC24HJ16GP304 BLOCK DIAGRAM PSV and Table Data Access Control Block Interrupt Controller 8 23 PCH PCU 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Data Latch 24 Instruction Decode and Control Control Signals to Various Blocks ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Buffer Pin Name Type Type AN0-AN12 I Analog CLKI I ST/CMOS CLKO O — OSC1 I ST/CMOS OSC2 I/O — SOSCI I ST/CMOS SOSCO O — CN0-CN30 I ST IC1-IC2 I ST IC7-IC8 OCFA I ST OC1-OC2 O — INT0 I ST INT1 ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name Type Type V P — CAP V P — Analog REF Analog REF VDD MCLR I VSS V P — DD Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels ...
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... STARTED WITH 16-BIT MICROCONTROLLERS Note 1: This data sheet summarizes the features of the PIC24HJ32GP202/204 PIC24HJ16GP304 family of devices not intended comprehensive ref- erence source. To complement the infor- mation in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 10 µ Tantalum R R1 MCLR C PIC24H 0.1 µF Ceramic 0.1 µF 10 Ω Ceramic 2.2.1 TANK CAPACITORS On boards with power traces running longer than six inches in length suggested to use a tank capacitor for integrated circuits including microcontrollers to supply a local power source ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 2.5 ICSP Pins The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP)™ and debugging pur- poses recommended to keep the trace length between the ICSP connector and the ICSP pins on the microcontroller as short as possible. If the ICSP con- ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 2.7 Oscillator Value Conditions on Device Start-up If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to ≤ 8 MHz for start-up with PLL enabled. This means that if the external oscillator frequency is outside this range, the application must start-up in FRC mode first ...
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... C compiler efficiency. For most instructions, the PIC24HJ32GP202/204 PIC24HJ16GP304 is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle result, three parameter instructions can be supported, allowing operations to be executed in a single cycle ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 FIGURE 3-1: PIC24HJ32GP202/204 AND PIC24HJ16GP304 CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Interrupt Controller 8 23 PCU 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Data Latch 24 Instruction Decode and Control Control Signals to Various Blocks ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 FIGURE 3-2: PIC24HJ32GP202/204 AND PIC24HJ16GP304 PROGRAMMER’S MODEL PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG — — — — — — SRH © 2011 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12 W13 W14/Frame Pointer W15/Stack Pointer ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 3.3 CPU Control Registers REGISTER 3-1: SR: CPU STATUS REGISTER U-0 U-0 U-0 — — — bit 15 (1) (2) R/W-0 R/W-0 R/W-0 (2) IPL<2:0> bit 7 Legend Clear only bit R = Readable bit S = Set only bit W = Writable bit ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-9 Unimplemented: Read as ‘ ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 3-2: CORCON: CORE CONTROL REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Clear only bit R = Readable bit W = Writable bit 0’ = Bit is cleared ‘x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ ...
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... ALU can be written to the W register array or a data memory location. Refer to the “16-bit MCU and DSC Programmer’s Ref- erence Manual” (DS70157) for more information on the SR bits affected by each instruction. The PIC24HJ32GP202/204 and PIC24HJ16GP304 CPU incorporates hardware support multiplication and division ...
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... This architecture also allows the direct access of program memory from the data space during code execution. FIGURE 4-1: PROGRAM MEMORY FOR PIC24HJ32GP202/204 AND PIC24HJ16GP304 DEVICES PIC24HJ32GP202/204 GOTO Instruction Reset Address Interrupt Vector Table ...
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... Program Memory ‘Phantom’ Byte (read as ‘0’) DS70289G-page 26 4.1.2 INTERRUPT AND TRAP VECTORS All PIC24HJ32GP202/204 and PIC24HJ16GP304 devices reserve the addresses between 0x00000 and organized in 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code ...
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... DATA MEMORY ORGANIZATION AND ALIGNMENT To maintain backward compatibility with PIC and improve data space memory usage efficiency, the PIC24HJ32GP202/204 and PIC24HJ16GP304 instruc- tion set supports both word and byte operations consequence of byte accessibility, all effective address calculations are internally scaled to step through word-aligned memory ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 FIGURE 4-3: DATA MEMORY MAP FOR PIC24HJ32GP202/204 AND PIC24HJ16GP304 DEVICES WITH 2 KB RAM MSB Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 2 Kbyte SRAM Space 0x0FFF 0x1001 0x1FFF 0x2001 0x8001 Optionally Mapped into Program Memory 0xFFFF DS70289G-page 28 LSB 16 bits ...
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TABLE 4-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...
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... CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CNPU2 006A CN30PUE CN29PUE — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJ32GP204 AND PIC24HJ16GP304 SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr ...
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TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr — — — INTCON1 0080 NSTDIS INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 — — ...
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TABLE 4-5: TIMER REGISTER MAP SFR Name SFR Bit 15 Bit 14 Bit 13 Bit 12 Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...
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TABLE 4-8: I2C1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr I2C1RCV 0200 — — — — I2C1TRN 0202 — — — — I2C1BRG 0204 — — — — I2C1CON 0206 I2CEN — I2CSIDL ...
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TABLE 4-11: PERIPHERAL PIN SELECT INPUT REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPINR0 0680 — — — RPINR1 0682 — — — — RPINR3 0686 — — — RPINR7 068E — — — ...
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... TABLE 4-13: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR PIC24HJ32GP204 AND PIC24HJ16GP304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RPOR0 06C0 — — — RPOR1 06C2 — — — RPOR2 06C4 — — — RPOR3 06C6 — — — RPOR4 06C8 — ...
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... TABLE 4-14: ADC1 REGISTER MAP FOR PIC24HJ32GP204 AND PIC24HJ16GP304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ADC1BUFC ...
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TABLE 4-15: ADC1 REGISTER MAP FOR PIC24HJ32GP202 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ...
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... ODCB 02CE ODCB15 ODCB14 ODCB13 ODCB12 Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. TABLE 4-19: PORTC REGISTER MAP FOR PIC24HJ32GP204 AND PIC24HJ16GP304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISC 02D0 — ...
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TABLE 4-20: SYSTEM CONTROL REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RCON 0740 TRAPR IOPUWR — — OSCCON 0742 — COSC<2:0> CLKDIV 0744 ROI DOZE<2:0> PLLFBD 0746 — — — — OSCTUN 0748 — ...
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... In addition to its use as a working register, the W15 register in the PIC24HJ32GP202/204 PIC24HJ16GP304 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 4-4 ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 4-23: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode File Register Direct Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified Register Indirect with Register Offset (Register Indexed) Register Indirect with Literal Offset 4.3.3 MOVE (MOV) INSTRUCTION Move instructions provide a greater degree of addressing flexibility than the other instructions ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 4.4 Interfacing Program and Data Memory Spaces The PIC24HJ32GP202/204 and PIC24HJ16GP304 architecture uses a 24-bit-wide program space and a 16 bit wide data space. The architecture is also a modified Harvard scheme, which means that the data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 FIGURE 4-5: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION (1) Program Counter (2) Table Operations (1) Program Space Visibility (Remapping) User/Configuration Space Select Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 4.4.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method to read or write the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only methods to read or write the upper 8 bits of a program space word as data ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 4.4.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access to the stored constant data from the data space without the need to use special instructions (such as TBLRDL/H) ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 NOTES: DS70289G-page 46 © 2011 Microchip Technology Inc. ...
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... Run-Time Self-Programming (RTSP) ICSP allows a PIC24HJ32GP202/204 PIC24HJ16GP304 device to be serially programmed while in the end application circuit. This is done with two lines for programming clock and programming data (one of the alternate programming pin pairs: PGECx/PGEDx), and three other lines for power (V ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 5.2 RTSP Operation The PIC24HJ32GP202/204 and PIC24HJ16GP304 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions time, and to program one row or one word at a time. The 8-row ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER (1) (1) R/SO-0 R/W-0 R/W-0 WR WREN WRERR bit 15 (1) U-0 R/W-0 U-0 — ERASE — bit 7 Legend Settable Only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 WR: Write Control bit 1 = Initiates a Flash memory program or erase operation ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 5-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 — — — bit 15 W-0 W-0 W-0 bit 7 Legend Settable Only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-8 Unimplemented: Read as ‘0’ ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 5.4.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY Programmers can program one row of program Flash memory at a time this necessary to erase the 8-row erase page that contains the desired row. The general process is: 1. Read eight rows of program (512 instructions) and store in data RAM. ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 EXAMPLE 5-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 MOV W0, NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 MOV W0, TBLPAG MOV #0x6000, W0 ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 6.0 RESETS Note 1: This data sheet summarizes the features of the PIC24HJ32GP202/204 PIC24HJ16GP304 families of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to “Section 8. Reset” (DS70192) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 6-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-0 U-0 TRAPR IOPUWR — bit 15 R/W-0 R/W-0 R/W-0 EXTR SWR SWDTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TRAPR: Trap Reset Flag bit Trap Conflict Reset has occurred ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 6-1: RCON: RESET CONTROL REGISTER bit 1 BOR: Brown-out Reset Flag bit Brown-out Reset has occurred Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit Power-on Reset has occurred Power-on Reset has not occurred Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 6.1 System Reset The PIC24HJ32GP202/204 and PIC24HJ16GP304 family of devices have two types of Reset: • Cold Reset • Warm Reset A cold Reset is the result of a Power-on Reset (POR Brown-out Reset (BOR cold Reset, the FNOSC configuration bits in the FOSC device configuration register selects the device clock source ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 FIGURE 6-2: SYSTEM RESET TIMING V POR POR 1 POR Reset 2 BOR Reset SYSRST Oscillator Clock FSCM Device Status Note 1: POR Reset: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until V crosses the V ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 6-2: OSCILLATOR DELAY Symbol V POR threshold POR T POR extension time POR V BOR threshold BOR T BOR extension time BOR T Programmable power-up time delay PWRT T Fail-Safe Clock Monitor Delay FSCM Note: When the device exits the Reset condi- tion (begins normal operation), the device operating parameters (voltage, frequency, temperature, etc ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 FIGURE 6-3: BROWN-OUT SITUATIONS V DD SYSRST V DD SYSRST V dips before PWRT expires SYSRST 6.3 External Reset (EXTR) The external Reset is generated by driving the MCLR pin low. The MCLR pin is a Schmitt trigger input with an additional glitch filter. Reset pulses that are longer than the minimum pulse-width will generate a Reset ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 6.7 Configuration Mismatch Reset To maintain the integrity of the peripheral pin select control registers, they are constantly monitored with shadow registers in hardware unexpected change in any of the registers occur (such as cell dis- turbances caused by ESD or other external events), a configuration mismatch Reset occurs. ...
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... Reset Sequence A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. The PIC24HJ32GP202/204 and PIC24HJ16GP304 and device clear its registers in response to a Reset, which forces the PC to zero. The microcontroller then begins the program execution at location 0x000000. The user ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 FIGURE 7-1: PIC24HJ32GP202/204 AND PIC24HJ16GP304 INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 7-1: INTERRUPT VECTORS Interrupt Vector Request (IRQ) IVT Address Number Number 8 0 0x000014 9 1 0x000016 10 2 0x000018 11 3 0x00001A 12 4 0x00001C 13 5 0x00001E 14 6 0x000020 15 7 0x000022 16 8 0x000024 17 9 0x000026 18 10 0x000028 19 11 0x00002A 20 12 0x00002C ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 7-1: INTERRUPT VECTORS (CONTINUED) Interrupt Vector Request (IRQ) IVT Address Number Number 54 46 0x000070 55 47 0x000072 56 48 0x000074 57 49 0x000076 58 50 0x000078 59 51 0x00007A 60 52 0x00007C 61 53 0x00007E 62 54 0x000080 63 55 0x000082 64 56 0x000084 65 57 0x000086 66 58 ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 7.3 Interrupt Control and Status Registers PIC24HJ32GP202/204 and PIC24HJ16GP304 devices implement a total of 17 registers for the interrupt controller: • Interrupt Control Register 1 (INTCON1) • Interrupt Control Register 2 (INTCON2) • Interrupt Flag Status Registers (IFSx) • Interrupt Enable Control Registers (IECx) • ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 7-1: SR: CPU STATUS REGISTER U-0 U-0 U-0 — — — bit 15 (3) (3) R/W-0 R/W-0 R/W-0 (2) (2) IPL2 IPL1 IPL0 bit 7 Legend Clear only bit R = Readable bit S = Set only bit W = Writable bit ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 IPL< ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 7-2: CORCON: CORE CONTROL REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Clear only bit R = Readable bit W = Writable bit 0’ = Bit is cleared ‘x = Bit is unknown bit 3 IPL3: CPU Interrupt Priority Level Status bit 3 ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 NSTDIS — — bit 15 U-0 R/W-0 U-0 — DIV0ERR — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 ALTIVT DISI — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 U-0 R/W-0 — — AD1IF bit 15 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-4 Unimplemented: Read as ‘0’ ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 U-0 U-0 R/W-0 — — INT2IF bit 15 R/W-0 R/W-0 U-0 IC8IF IC7IF — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-4 Unimplemented: Read as ‘0’ ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 7-7: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-2 Unimplemented: Read as ‘0’ ...
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... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 7-8: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 U-0 R/W-0 — — AD1IE bit 15 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-4 Unimplemented: Read as ‘0’ ...
Page 75
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 7-8: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2011 Microchip Technology Inc. ...
Page 76
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 7-9: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 U-0 U-0 R/W-0 — — INT2IE bit 15 R/W-0 R/W-0 U-0 IC8IE IC7IE — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 77
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 7-10: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-2 Unimplemented: Read as ‘0’ ...
Page 78
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 7-11: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 — T1IP<2:0> bit 15 U-0 R/W-1 R/W-0 — IC1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 79
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 7-12: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 — T2IP<2:0> bit 15 U-0 R/W-1 R/W-0 — IC2IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 80
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 7-13: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 — U1RXIP<2:0> bit 15 U-0 R/W-1 R/W-0 — SPI1EIP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 81
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 7-14: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — AD1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 AD1IP< ...
Page 82
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 7-15: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 — CNIP<2:0> bit 15 U-0 R/W-1 R/W-0 — MI2C1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 83
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 7-16: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 R/W-1 R/W-0 — IC8IP<2:0> bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC8IP< ...
Page 84
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 7-17: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — INT2IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 INT2IP< ...
Page 85
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 7-18: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — U1EIP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 U1EIP< ...
Page 86
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 7-19: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 — — — bit 15 U-0 R-0 R-0 — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR< ...
Page 87
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 7.4 Interrupt Setup Procedures 7.4.1 INITIALIZATION To configure an interrupt source at initialization: 1. Set the NSTDIS bit (INTCON1<15>) if nested interrupts are not desired. 2. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source ...
Page 88
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 NOTES: DS70289G-page 88 © 2011 Microchip Technology Inc. ...
Page 89
... Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” this data sheet for device-specific register and bit information. FIGURE 8-1: PIC24HJ32GP202/204 AND PIC24HJ16GP304 OSCILLATOR SYSTEM DIAGRAM Primary Oscillator OSC1 ( OSC2 POSCMD< ...
Page 90
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 8.1 CPU Clocking System The PIC24HJ32GP202/204 and PIC24HJ16GP304 devices provide the following seven system clock options. • Fast RC (FRC) Oscillator • FRC Oscillator with PLL • Primary (XT EC) Oscillator • Primary Oscillator with PLL • Secondary (LP) Oscillator • Low-Power RC (LPRC) Oscillator • ...
Page 91
... PLL” being the selected oscillator mode. • If PLLPRE<4:0> then This yields a VCO input of 10 MHz, which is within the acceptable range of 0.8-8 MHz. FIGURE 8-2: PIC24HJ32GP202/204 AND PIC24HJ16GP304 PLL BLOCK DIAGRAM Source (Crystal, External Clock or Internal RC) Note 1: This frequency range must be satisfied at all times. TABLE 8-1: ...
Page 92
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R-0 R-0 — COSC<2:0> bit 15 R/W-0 R/W-0 R-0 CLKLOCK IOLOCK LOCK bit 7 Legend Value set from Configuration bits on POR R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ ...
Page 93
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER bit 3 CF: Clock Fail Detect bit (read/clear by application FSCM has detected clock failure 0 = FSCM has not detected clock failure bit 2 Unimplemented: Read as ‘0’ bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit 1 = Enable secondary oscillator ...
Page 94
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 8-2: CLKDIV: CLOCK DIVISOR REGISTER R/W-0 R/W-0 R/W-1 ROI DOZE<2:0> bit 15 R/W-0 R/W-1 U-0 PLLPOST<1:0> — bit 7 Legend Value set from Configuration bits on POR R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ROI: Recover on Interrupt bit ...
Page 95
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 8-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) 111111111 = 513 • ...
Page 96
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 8-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN< ...
Page 97
... Applications are free to switch among any of the four clock sources (Primary, LP, FRC and LPRC) under software control at any time. To limit the possible side effects of this flexibility, PIC24HJ32GP202/204 and PIC24HJ16GP304 devices have a safeguard lock built into the switch process. Note: Primary Oscillator mode has three different ...
Page 98
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 NOTES: DS70289G-page 98 © 2011 Microchip Technology Inc. ...
Page 99
... Put the device into Idle mode © 2011 Microchip Technology Inc. 9.2 Instruction-Based Power-Saving Modes PIC24HJ32GP202/204 and PIC24HJ16GP304 devices and have two special power-saving modes that are entered through the execution of a special PWRSAV instruction. Sleep mode stops clock operation and halts all code execution ...
Page 100
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 9.2.2 IDLE MODE The following occur in Idle mode: • The CPU stops executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 9 ...
Page 101
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 9-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 U-0 U-0 R/W-0 — — T3MD bit 15 R/W-0 U-0 R/W-0 I2C1MD — U1MD bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 102
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 9-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 R/W-0 R/W-0 U-0 IC8MD IC7MD — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 IC8MD: Input Capture 8 Module Disable bit ...
Page 103
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 10.0 I/O PORTS Note 1: This data sheet summarizes the features of the PIC24HJ32GP202/204 PIC24HJ16GP304 family of devices. However not intended comprehensive reference source. To complement the information in this data sheet, refer to “Section 10. I/O Ports” (DS70193) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www ...
Page 104
... Input Change Notification The input change notification function of the I/O ports allows the PIC24HJ16GP304 devices to generate interrupt requests to the processor in response to a change-of-state on selected input pins. This feature can detect input change-of-states even in Sleep mode, when the clocks are disabled. Depending on the device ...
Page 105
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 10.6 Peripheral Pin Select A major challenge in general purpose devices is providing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins. The challenge is even greater on low-pin count devices application where more than one peripheral must be assigned to a single pin, inconve- nient workarounds in application code or a complete redesign may be the only option ...
Page 106
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 10-1: REMAPPABLE PERIPHERAL INPUTS Input Name External Interrupt 1 External Interrupt 2 Timer 2 External Clock Timer 3 External Clock Input Capture 1 Input Capture 2 Input Capture 7 Input Capture 8 Output Compare Fault A UART 1 Receive UART 1 Clear To Send SPI 1 Data Input SPI 1 Clock Input ...
Page 107
... Programming IOL1WAY allows user applications unlimited access (with the proper use of the unlock sequence) to the peripheral pin select registers. 10.7 Peripheral Pin Select Registers The PIC24HJ32GP202/204 and PIC24HJ16GP304 devices implement 17 registers for remappable peripheral configuration: • Input Remappable Peripheral Registers (9) built-in C • ...
Page 108
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 10-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 109
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 10-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 110
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 10-4: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 111
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 10-5: RPIR10: PERIPHERAL PIN SELECT INPUT REGISTER 10 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 112
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 10-6: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ ...
Page 113
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 10-7: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 114
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 10-8: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 115
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 10-9: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ ...
Page 116
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 10-11: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 117
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 10-13: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 118
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 10-15: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 119
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 10-17: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 120
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 10-19: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 121
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 10-21: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 122
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 NOTES: DS70289G-page 122 © 2011 Microchip Technology Inc. ...
Page 123
... TIMER1 Note 1: This data sheet summarizes the features of the PIC24HJ32GP202/204 PIC24HJ16GP304 family of devices not intended comprehensive ref- erence source. To complement the infor- mation in this data sheet, refer to “Section 11. Timers” (DS702064) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www ...
Page 124
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE TCKPS<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 ...
Page 125
... TIMER2/3 FEATURE Note 1: This data sheet summarizes the features of the PIC24HJ32GP202/204 PIC24HJ16GP304 family of devices not intended comprehensive ref- erence source. To complement the infor- mation in this data sheet, refer to “Section 11. Timers” (DS70206) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www ...
Page 126
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 FIGURE 12-1: TIMER2/3 (32-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T3IF 0 (2) ADC Event Trigger Equal MSb Reset Read TMR2 Write TMR2 Data Bus<15:0> Note 1: The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register ...
Page 127
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 FIGURE 12-2: TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal © 2011 Microchip Technology Inc. 1x Gate Sync TMR2 Sync Comparator PR2 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TCS TGATE DS70289G-page 127 ...
Page 128
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 12-1: T2CON CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE TCKPS<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer2 On bit When T32 = Starts 32-bit Timer2/3 ...
Page 129
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 12-2: T3CON CONTROL REGISTER R/W-0 U-0 R/W-0 (2) TON — TSIDL bit 15 U-0 R/W-0 R/W-0 (2) — TGATE TCKPS<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set (2) bit 15 TON: Timer3 On bit 1 = Starts 16-bit Timer3 0 = Stops 16-bit Timer3 bit 14 Unimplemented: Read as ‘ ...
Page 130
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 NOTES: DS70289G-page 130 © 2011 Microchip Technology Inc. ...
Page 131
... INPUT CAPTURE Note 1: This data sheet summarizes the features of the PIC24HJ32GP202/204 PIC24HJ16GP304 family of devices not intended comprehensive ref- erence source. To complement the infor- mation in this data sheet, refer to “Section 12. Input Capture” (DS70198) of the “dsPIC33F/PIC24H Family Refer- ence Manual”, which is available from the Microchip website (www ...
Page 132
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 13.1 Input Capture Registers REGISTER 13-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER U-0 U-0 R/W-0 — — ICSIDL bit 15 R/W-0 R/W-0 R/W-0 ICTMR ICI<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 133
... OUTPUT COMPARE Note 1: This data sheet summarizes the features of the PIC24HJ32GP202/204 PIC24HJ16GP304 family of devices. However not intended com- prehensive reference source. To comple- ment the information in this data sheet, refer to “Section 13. Output Compare” (DS70209) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www ...
Page 134
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 14.1 Output Compare Modes Configure the Output Compare modes by setting the appropriate Output Compare Mode bits (OCM<2:0>) in the Output Compare Control register (OCxCON<2:0>). Table 14-1 lists the different bit settings for the Output Compare modes. Figure 14-2 illustrates the output compare operation for various modes ...
Page 135
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 14.2 Output Compare Register REGISTER 14-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER U-0 U-0 R/W-0 — — OCSIDL bit 15 U-0 U-0 U-0 — — — bit 7 Legend Cleared in Hardware R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘ ...
Page 136
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 NOTES: DS70289G-page 136 © 2011 Microchip Technology Inc. ...
Page 137
... SERIAL PERIPHERAL INTERFACE (SPI) Note 1: This data sheet summarizes the features of the PIC24HJ32GP202/204 PIC24HJ16GP304 family of devices. However not intended com- prehensive reference source. To comple- ment the information in this data sheet, refer to “Section 18. Serial Peripheral Interface (SPI™)” (DS70206) of the “dsPIC33F/PIC24H Family Reference Manual” ...
Page 138
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 15-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 SPIEN — SPISIDL bit 15 U-0 R/C-0 U-0 — SPIROV — bit 7 Legend Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 SPIEN: SPIx Enable bit ...
Page 139
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 15-2: SPI CON1: SPIx CONTROL REGISTER 1 X U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 (2) SSEN CKP MSTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 140
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 15-2: SPI CON1: SPIx CONTROL REGISTER 1 (CONTINUED) X bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 • • • 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode) ...
Page 141
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 15-3: SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 FRMEN SPIFSD FRMPOL bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support enabled (SSx pin used as frame sync pulse input/output) ...
Page 142
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 NOTES: DS70289G-page 142 © 2011 Microchip Technology Inc. ...
Page 143
... INTER-INTEGRATED 2 CIRCUIT™ (I C™) Note 1: This data sheet summarizes the features of the PIC24HJ32GP202/204 PIC24HJ16GP304 family of devices. However not intended com- prehensive reference source. To comple- ment the information in this data sheet, refer to “Section 19. Inter-Integrated 2 Circuit™ (I C™)” (DS70195) of the “ ...
Page 144
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 2 FIGURE 16-1: I C™ BLOCK DIAGRAM ( Shift SCLx Clock SDAx Shift Clock BRG Down Counter DS70289G-page 144 = 1) X I2CxRCV I2CxRSR LSb Address Match Match Detect I2CxADD Start and Stop Bit Detect Start and Stop Bit Generation Collision Detect ...
Page 145
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 I2CEN — I2CSIDL bit 15 R/W-0 R/W-0 R/W-0 GCEN STREN ACKDT bit 7 Legend Unimplemented bit, read as ‘0’ Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables the I2Cx module ...
Page 146
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I Value that will be transmitted when the software initiates an Acknowledge sequence Send NACK during Acknowledge 0 = Send ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit ...
Page 147
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER R-0 HSC R-0 HSC U-0 ACKSTAT TRSTAT — bit 15 R/C-0 HS R/C-0 HS R-0 HSC IWCOL I2COV D_A bit 7 Legend Unimplemented bit, read as ‘0’ Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ...
Page 148
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 2 R_W: Read/Write Information bit (when operating Read – ...
Page 149
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 16-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-10 Unimplemented: Read as ‘0’ ...
Page 150
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 NOTES: DS70289G-page 150 © 2011 Microchip Technology Inc. ...
Page 151
... The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in the PIC24HJ32GP202/204 PIC24HJ16GP304 device family. The UART is a full-duplex asynchronous system communicate with peripheral devices, such as personal computers, LIN, RS-232 and RS-485 interfaces. The module also supports a hardware flow control option with the UxCTS and UxRTS pins and ® ...
Page 152
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 17-1: UxMODE: UART R/W-0 U-0 R/W-0 (1) UARTEN — USIDL bit 15 R/W-0 HC R/W-0 R/W-0, HC WAKE LPBACK ABAUD bit 7 Legend Hardware Clearable R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 UARTEN: UARTx Enable bit 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> ...
Page 153
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 17-1: UxMODE: UART bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits ...
Page 154
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 17-2: U STA: UART x R/W-0 R/W-0 R/W-0 UTXISEL1 UTXINV UTXISEL0 bit 15 R/W-0 R/W-0 R/W-0 URXISEL<1:0> ADDEN bit 7 Legend Hardware cleared R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15,13 UTXISEL<1:0>: Transmission Interrupt Mode Selection bits 11 = Reserved ...
Page 155
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 17-2: U STA: UART x bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect 0 = Address Detect mode disabled bit 4 RIDLE: Receiver Idle bit (read-only Receiver is Idle ...
Page 156
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 NOTES: DS70289G-page 156 © 2011 Microchip Technology Inc. ...
Page 157
... The actual number of analog input pins and external voltage reference input configuration will depend on the specific device. Refer to the device data sheet for further details. A block diagram of ADC for PIC24HJ16GP304 and in PIC24HJ32GP204 devices is shown in block diagram of the ADC for the PIC24HJ32GP202 ...
Page 158
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 FIGURE 18-1: ADC1 MODULE BLOCK DIAGRAM FOR PIC24HFJ16GP304 AND PIC24HJ32GP204 DEVICES AN0 AN12 CHANNEL SCAN CH0SB<4:0> CH0SA<4:0> CH0 CSCNA AN1 V REFL CH0NA CH0NB AN0 AN3 CH123SA CH123SB (2) CH1 AN6 AN9 V REFL CH123NA CH123NB AN1 AN4 CH123SA CH123SB (2) CH2 ...
Page 159
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 FIGURE 18-2: ADC1 MODULE BLOCK DIAGRAM FOR PIC24HJ32GP202 DEVICES AN0 AN12 CHANNEL SCAN CH0SB<4:0> CH0SA<4:0> CH0 CSCNA AN1 V REFL CH0NA CH0NB AN0 AN3 CH123SA CH123SB (2) CH1 AN9 V REFL CH123NA CH123NB AN1 AN4 CH123SA CH123SB (2) CH2 AN10 V REFL CH123NA CH123NB ...
Page 160
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 FIGURE 18-3: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADC Internal (2) RC Clock OSC Note 1: Refer to Figure 8-2 for the derivation the clock frequency See the ADC Electrical Characteristics for the exact RC Clock value. DS70289G-page 160 AD1CON3<5:0> 6 ADC Conversion Clock Multiplier ...
Page 161
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 18-1: AD1CON1: ADC1 CONTROL REGISTER 1 R/W-0 U-0 R/W-0 ADON — ADSIDL bit 15 R/W-0 R/W-0 R/W-0 SSRC<2:0> bit 7 Legend Cleared by hardware R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ADON: ADC Operating Mode bit 1 = ADC module is operating ...
Page 162
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 18-1: AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED) bit 2 ASAM: ADC Sample Auto-Start bit 1 = Sampling begins immediately after last conversion. SAMP bit is auto-set 0 = Sampling begins when SAMP bit is set bit 1 SAMP: ADC Sample Enable bit 1 = ADC sample-and-hold amplifiers are sampling 0 = ADC sample-and-hold amplifiers are holding If ASAM = 0, software can write ‘ ...
Page 163
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 18-2: AD1CON2: ADC1 CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 VCFG<2:0> bit 15 R-0 U-0 R/W-0 BUFS — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 VCFG<2:0>: Converter Voltage Reference Configuration bits ADREF+ A 000 ...
Page 164
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 18-3: AD1CON3: ADC1 CONTROL REGISTER 3 R/W-0 U-0 U-0 ADRC — — bit 15 U-0 U-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ADRC: ADC Conversion Clock Source bit 1 = ADC internal RC clock ...
Page 165
... Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 10 = Reserved 01 = CH1, CH2, CH3 negative input CH1, CH2, CH3 negative input is V PIC24HJ32GP204 and PIC24HJ16GP304 devices only: If AD12B = Reserved 10 = Reserved 01 = Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 ...
Page 166
... Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 10 = Reserved 01 = CH1, CH2, CH3 negative input CH1, CH2, CH3 negative input is V PIC24HJ32GP204 and PIC24HJ16GP304 devices only: If AD12B = Reserved 10 = Reserved 01 = Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 ...
Page 167
... Channel 0 negative input is AN1 0 = Channel 0 negative input is V bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits PIC24HJ32GP204 and PIC24HJ16GP304 devices only: 01100 = Channel 0 positive input is AN12 • • • 00010 = Channel 0 positive input is AN2 ...
Page 168
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 18-5: AD1CHS0: ADC1 INPUT CHANNEL 0 SELECT REGISTER (CONTINUED) bit 4-0 CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits PIC24HJ32GP204 and PIC24HJ16GP304 devices only: 01100 = Channel 0 positive input is AN12 • • • 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 ...
Page 169
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 18-6: AD1CSSL: ADC1 INPUT SCAN SELECT REGISTER LOW U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 CSS7 CSS6 CSS5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 170
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 NOTES: DS70289G-page 170 © 2011 Microchip Technology Inc. ...
Page 171
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 19.0 SPECIAL FEATURES Note: This data sheet summarizes the features of the PIC24HJ32GP202/204 PIC24HJ16GP304 devices not intended reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Manual”. Please see the Microchip web site (www.microchip.com) for the latest ...
Page 172
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 19-2: PIC24HJ32GP202/204 AND PIC24HJ16GP304 CONFIGURATION BITS DESCRIPTION RTSP Bit Field Register Effect BWRP FBS Immediate Boot Segment Program Flash Write Protection BSS<2:0> FBS Immediate PIC24HJ32GP202 and PIC24HJ32GP204 Devices Only BSS<2:0> FBS Immediate PIC24HJ16GP304 Devices Only GSS<1:0> FGS ...
Page 173
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 19-2: PIC24HJ32GP202/204 AND PIC24HJ16GP304 CONFIGURATION BITS DESCRIPTION (CONTINUED) RTSP Bit Field Register Effect FCKSM<1:0> FOSC Immediate Clock Switching Mode bits IOL1WAY FOSC Immediate Peripheral Pin Select Configuration OSCIOFNC FOSC Immediate OSC2 Pin Function bit (except in XT and HS modes) POSCMD< ...
Page 174
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 19-2: PIC24HJ32GP202/204 AND PIC24HJ16GP304 CONFIGURATION BITS DESCRIPTION (CONTINUED) RTSP Bit Field Register Effect ICS<1:0> FICD Immediate ICD Communication Channel Select bits DS70289G-page 174 Description 11 = Communicate on PGEC1 and PGED1 10 = Communicate on PGEC2 and PGED2 01 = Communicate on PGEC3 and PGED3 00 = Reserved, do not use ...
Page 175
... To simplify system design, all devices in the PIC24HJ32GP202/204 PIC24HJ16GP304 family incorporate an on-chip regu- lator that allows the device to run its core logic from The regulator provides power to the core from the other V pins ...
Page 176
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 19.4 Watchdog Timer (WDT) For PIC24HJ32GP202/204 and PIC24HJ16GP304 devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. 19.4.1 PRESCALER/POSTSCALER The nominal WDT clock source from LPRC is 32 kHz. This feeds a prescaler than can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation ...
Page 177
... Detailed information on this interface will be provided in future revisions of the document. 19.6 Code Protection and CodeGuard™ Security The PIC24HJ32GP202/204 and PIC24HJ16GP304 product families offer the intermediate implementation of CodeGuard Security. CodeGuard Security allows multiple parties to securely share resources (memory, TABLE 19-3: ...
Page 178
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 19.7 In-Circuit Serial Programming PIC24HJ32GP202/204 and PIC24HJ16GP304 family microcontrollers can be serially programmed while in the end application circuit. This is done with two lines for clock and data, and three other lines for power, ground and the programming sequence. Serial pro- ...
Page 179
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 20.0 INSTRUCTION SET SUMMARY Note: This data sheet summarizes the features of this group of PIC24HJ32GP202/204 and PIC24HJ16GP304 devices not intended comprehensive refer- ence source. To complement the informa- tion in this data sheet, refer to the “dsPIC33F/PIC24H Family Manual”. Please see the Microchip web site (www ...
Page 180
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 20-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” Optional field or operation <n:m> Register bit field .b Byte mode selection .d Double Word mode selection ...
Page 181
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 20-2: INSTRUCTION SET OVERVIEW Base Assembly Instr Assembly Syntax Mnemonic # ADD f 1 ADD ADD f,WREG ADD #lit10,Wn ADD Wb,Ws,Wd ADD Wb,#lit5,Wd 2 ADDC ADDC f ADDC f,WREG ADDC #lit10,Wn ADDC Wb,Ws,Wd ADDC Wb,#lit5,Wd 3 AND AND f AND f,WREG AND #lit10,Wn ...
Page 182
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 20-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 12 BTST BTST f,#bit4 BTST.C Ws,#bit4 BTST.Z Ws,#bit4 BTST.C Ws,Wb BTST.Z Ws,Wb 13 BTSTS BTSTS f,#bit4 BTSTS.C Ws,#bit4 BTSTS.Z Ws,#bit4 14 CALL CALL lit23 CALL Wn 15 CLR CLR f CLR ...
Page 183
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 20-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 35 INC INC f INC f,WREG INC Ws,Wd 36 INC2 INC2 f INC2 f,WREG INC2 Ws,Wd 37 IOR IOR f IOR f,WREG IOR #lit10,Wn IOR Wb,Ws,Wd IOR Wb,#lit5,Wd 38 LNK LNK #lit14 39 LSR ...
Page 184
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 20-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 47 RCALL RCALL Expr RCALL Wn 48 REPEAT REPEAT #lit14 REPEAT Wn 49 RESET RESET 50 RETFIE RETFIE 51 RETLW RETLW #lit10,Wn 52 RETURN RETURN 53 RLC RLC f RLC f,WREG RLC Ws,Wd 54 RLNC ...
Page 185
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 20-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 66 TBLRDL TBLRDL Ws,Wd 67 TBLWTH TBLWTH Ws,Wd 68 TBLWTL TBLWTL Ws,Wd 69 ULNK ULNK 70 XOR XOR f XOR f,WREG XOR #lit10,Wn XOR Wb,Ws,Wd XOR Wb,#lit5, Ws,Wnd © 2011 Microchip Technology Inc. ...
Page 186
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 NOTES: DS70289G-page 186 © 2011 Microchip Technology Inc. ...
Page 187
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 21.0 DEVELOPMENT SUPPORT ® The PIC microcontrollers and dsPIC controllers are supported with a full range of software and hardware development tools: • Integrated Development Environment ® - MPLAB IDE Software • Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C for Various Device Families ...
Page 188
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 21.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal control- lers. These compilers provide powerful integration capabilities, superior code optimization and ease of use ...
Page 189
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 21.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulat- ® ing the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller ...
Page 190
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 21.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers. The full featured ® Windows programming interface supports baseline ...
Page 191
... This section provides an overview of PIC24HJ32GP202/204 and PIC24HJ16GP304 electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24HJ32GP202/204 and PIC24HJ16GP304 family are listed below. Exposure to these maximum rating conditions for extended periods can affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied ...
Page 192
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 22.1 DC Characteristics TABLE 22-1: OPERATING MIPS VS. VOLTAGE V Range DD Characteristic (in Volts) 3.0-3.6V 3.0-3.6V TABLE 22-2: THERMAL OPERATING CONDITIONS Rating Industrial Temperature Devices Operating Junction Temperature Range Operating Ambient Temperature Range Extended Temperature Devices Operating Junction Temperature Range Operating Ambient Temperature Range ...
Page 193
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 22-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristic No. Operating Voltage DC10 Supply Voltage V — DD DC12 V RAM Data Retention Voltage DR DC16 V V Start Voltage POR DD to ensure internal Power-on Reset signal DC17 S V Rise Rate VDD DD to ensure internal ...
Page 194
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 22-5: DC CHARACTERISTICS: OPERATING CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. (2) Operating Current ( DC20d 20 30 DC20a 19 22 DC20b 19 25 DC20c 19 30 DC21d 28 40 DC21a 27 30 DC21b 27 32 DC21c 27 36 DC22d 33 50 DC22a 33 40 DC22b 33 40 DC22c 33 50 DC23d ...
Page 195
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 22-6: DC CHARACTERISTICS: IDLE CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. Idle Current (I ): Core OFF Clock ON Base Current IDLE DC40d 7 20 DC40a 6 7 DC40b 6 10 DC40c 6 20 DC41d 10 20 DC41a 8 9 DC41b 8 10 DC41c 8 20 DC42d 11 20 DC42a 10 10 ...
Page 196
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 22-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. (2) Power-Down Current ( DC60d 55 500 DC60a 63 300 DC60b 85 350 DC60c 146 600 DC61d 8 15 DC61a 2 3 DC61b 2 2 DC61c 3 5 Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated. ...
Page 197
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 22-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristic No. V Input Low Voltage IL DI10 I/O pins DI15 MCLR DI16 I/O Pins with OSC1 or SOSCI DI18 SDAx, SCLx DI19 SDAx, SCLx V Input High Voltage IH DI20 I/O Pins Not 5V Tolerant ...
Page 198
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 22-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) DC CHARACTERISTICS Param Symbol Characteristic No. I Input Leakage Current IL DI50 I/O Pins 5V Tolerant DI51 I/O Pins Not 5V Tolerant DI51a I/O Pins Not 5V Tolerant DI51b I/O Pins Not 5V Tolerant DI51c I/O Pins Not 5V Tolerant ...
Page 199
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 22-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) DC CHARACTERISTICS Param Symbol Characteristic No. I Input Low Injection Current ICL DI60a I Input High Injection Current ICH DI60b ∑I Total Input Injection Current ICT DI60c (sum of all I/O and control pins) Note 1: Data in “ ...
Page 200
... PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 22-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristic No. V Output Low Voltage OL DO10 I/O ports DO16 OSC2/CLKO V Output High Voltage OH DO20 I/O ports DO26 OSC2/CLKO TABLE 22-11: ELECTRICAL CHARACTERISTICS: BOR DC CHARACTERISTICS Param Symbol Characteristic No. ...