PIC16C770-I/SO Microchip Technology, PIC16C770-I/SO Datasheet - Page 87

• Manufacturer Part Number: PIC16C770-I/SO
• Description: IC MCU OTP 2KX14 A/D PWM 20-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C770-I/SO

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI
• Number Of I /o: 15
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Controller Family/series: PIC16C
• No. Of I/o's: 16
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGAC164028 - MODULE SKT PROMATEII 20SOIC/DIP309-1013 - ADAPTER 20-SOIC TO 20-DIP309-1012 - ADAPTER 20-SOIC TO 20-DIP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: PIC16C770I/SO

FIGURE 9-15:
9.2.10
To initiate a START condition, the user sets the START
condition enable bit, SEN (SSPCON2<0>). If the SDA
and SCL pins are sampled high, indicating that the bus
is available, the baud rate generator is loaded with the
contents of SSPADD<6:0> and starts its count. If SCL
and SDA are both sampled high when the baud rate
generator times out (T
available, the SDA pin is driven low. The SDA transition
from high to low while SCL is high is the START condi-
tion. This causes the S bit (SSPSTAT<3>) to be set.
When the S bit is set, the baud rate generator is
reloaded with the contents of SSPADD<6:0> and
resumes its count. When the baud rate generator times
out (T
rent with the following events:
• The SEN bit (SSPCON2<0>) is automatically
• The baud rate generator is suspended leaving the
• The SSPIF flag is set.
FIGURE 9-16:
2002 Microchip Technology Inc.
cleared by hardware,
SDA line held low.
BRG
) the START condition is complete, concur-
I
CONDITION TIMING
2
C MASTER MODE START
SDA
SCL
BRG
value
BRG
reload
Write to SEN bit occurs here.
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
FIRST START BIT TIMING
BRG
) indicating the bus is still
03h
SDA
SCL
DX
SCL de-asserted but slave holds
SCL low (clock arbitration)
02h
SCL is sampled high, reload takes
place, and BRG starts its count.
Advance Information
SDA = 1,
SCL = 1
T
BRG
01h
Set S bit (SSPSTAT<3>)
T
S
BRG
BRG decrements
(on Q2 and Q4 cycles)
00h (hold off)
DX-1
At completion of START bit,
Hardware clears SEN bit
9.2.10.1
If the user writes the SSPBUF when a START
sequence is in progress, the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
and sets SSPIF bit
Note:
Note:
PIC16C717/770/771
T
Write to SSPBUF occurs here
BRG
1st Bit
If at the beginning of START condition, the
SDA and SCL pins are already sampled
low, or if during the START condition, the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs.
Thus, the Bus Collision Interrupt Flag
(BCLIF) is set, the START condition is
aborted, and the I
its IDLE state.
WCOL STATUS FLAG
Because queueing of events is not
allowed, writing to the lower five bits of
SSPCON2 is disabled until the START
condition is complete.
SCL allowed to transition high
T
03h
BRG
02h
2nd Bit
2
C module is RESET into
DS41120B-page 85