PIC16C770-I/SO Microchip Technology, PIC16C770-I/SO Datasheet - Page 130

• Manufacturer Part Number: PIC16C770-I/SO
• Description: IC MCU OTP 2KX14 A/D PWM 20-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C770-I/SO

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI
• Number Of I /o: 15
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Controller Family/series: PIC16C
• No. Of I/o's: 16
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGAC164028 - MODULE SKT PROMATEII 20SOIC/DIP309-1013 - ADAPTER 20-SOIC TO 20-DIP309-1012 - ADAPTER 20-SOIC TO 20-DIP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: PIC16C770I/SO

PIC16C717/770/771
12.10.1
External interrupt on RB0/INT pin is edge triggered:
either rising if bit INTEDG (OPTION_REG<6>) is set,
or falling, if the INTEDG bit is clear. When a valid edge
appears
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service rou-
tine before re-enabling this interrupt. The INT interrupt
can wake-up the processor from SLEEP, if bit INTE was
set prior to going into SLEEP. The status of global inter-
rupt enable bit GIE decides whether or not the proces-
sor branches to the interrupt vector following wake-up.
See Section 12.13 for details on SLEEP mode.
12.10.2
An overflow (FFh
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 2.2.2.3)
12.10.3
An input change on PORTB<7:0> sets flag bit RBIF
(INTCON<0>). The PORTB pin(s) which can individu-
ally generate interrupt is selectable in the IOCB regis-
ter. The interrupt can be enabled/disabled by setting/
clearing
(Section 2.2.2.3)
EXAMPLE 12-1:
DS41120B-page 128
#define
#define
#define
org
MOVWF
MOVF
MOVWF
MOVF
MOVWF
:
(Interrupt Service Routine)
:
MOVF
MOVWF
MOVF
MOVWF
SWAPF
SWAPF
RETFIE
on
INT INTERRUPT
TMR0 INTERRUPT
PORTB INTCON CHANGE
enable
W_TEMP
STATUS_TEMP
PCLATH_TEMP
0x04
STATUS,w
STATUS_TEMP
PCLATH,w
PCLATH_TEMP
PCLATH_TEMP,w
PCLATH
STATUS_TEMP,w
STATUS
W_TEMP,f
W_TEMP,w
W_TEMP
the
00h) in the TMR0 register will set
RB0/INT
Saving STATUS, W, and PCLATH Registers in RAM
bit
RBIE
pin,
0x70
0x71
0x72
; start at Interrupt Vector
; Save W register
; save STATUS
; save PCLATH
;
; swapf loads W without affecting STATUS flags
flag
(INTCON<4>).
bit
INTF
12.11 Context Saving During Interrupts
During an interrupt, only the PC is saved on the stack.
At the very least, W and STATUS should be saved to
preserve the context for the interrupted program. All
registers that may be corrupted by the ISR, such as
PCLATH or FSR, should be saved.
Example 12-1 stores and restores the STATUS, W and
PCLATH registers. The register, W_TEMP, is defined in
Common RAM, the last 16 bytes of each bank that may
be accessed from any bank. The STATUS_TEMP and
PCLATH_TEMP are defined in bank 0.
The example:
a)
b)
c)
d)
e)
f)
g)
Note
PCLATH_TEMP are defined in the common RAM area
(70h - 7Fh) to avoid register bank switching during con-
text save and restore.
Stores the W register.
Stores the STATUS register in bank 0.
Stores the PCLATH register in bank 0.
Executes the ISR code.
Restores the PCLATH register.
Restores the STATUS register
Restores W.
that
W_TEMP,
2002 Microchip Technology Inc.
STATUS_TEMP
and