PIC18F26K20-I/SP Microchip Technology, PIC18F26K20-I/SP Datasheet - Page 425

• Manufacturer Part Number: PIC18F26K20-I/SP
• Description: IC PIC MCU FLASH 32KX16 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26K20-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: CCP/ECCP/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 64 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Timer1 .............................................................................. 157
Timer2 .............................................................................. 165
Timer3 .............................................................................. 167
Timing Diagrams
© 2008 Microchip Technology Inc.
Source Select (T0CS Bit) ......................................... 154
Switching Prescaler Assignment .............................. 155
16-Bit Read/Write Mode ........................................... 160
Associated Registers ............................................... 163
Asynchronous Counter Mode .................................. 159
Interrupt .................................................................... 161
Operation ................................................................. 158
Oscillator .......................................................... 157, 160
Oscillator Layout Considerations ............................. 161
Overflow Interrupt .................................................... 157
Prescaler .................................................................. 159
Resetting, Using the CCP Special Event Trigger ..... 161
Special Event Trigger (ECCP) ................................. 172
TMR1H Register ...................................................... 157
TMR1L Register ....................................................... 157
Use as a Real-Time Clock ....................................... 162
Associated Registers ............................................... 166
Interrupt .................................................................... 166
Operation ................................................................. 165
Output ...................................................................... 166
16-Bit Read/Write Mode ........................................... 169
Associated Registers ............................................... 170
Operation ................................................................. 168
Oscillator .......................................................... 167, 169
Overflow Interrupt ............................................ 167, 169
Special Event Trigger (CCP) .................................... 170
TMR3H Register ...................................................... 167
TMR3L Register ....................................................... 167
A/D Conversion ........................................................ 397
Acknowledge Sequence .......................................... 226
Asynchronous Reception ......................................... 241
Asynchronous Transmission .................................... 236
Asynchronous Transmission (Back to Back) ........... 237
Auto Wake-up Bit (WUE) During Normal Operation 251
Auto Wake-up Bit (WUE) During Sleep ................... 251
Automatic Baud Rate Calculator .............................. 250
Baud Rate Generator with Clock Arbitration ............ 220
BRG Reset Due to SDA Arbitration During
Brown-out Reset (BOR) ........................................... 383
Bus Collision During a Repeated Start Condition
Bus Collision During a Repeated Start Condition
Bus Collision During a Start Condition (SCL = 0) .... 229
Bus Collision During a Stop Condition (Case 1) ...... 231
Bus Collision During a Stop Condition (Case 2) ...... 231
Bus Collision During Start Condition (SDA only) ..... 228
Bus Collision for Transmit and Acknowledge ........... 227
Capture/Compare/PWM (CCP) ................................ 385
CLKO and I/O .......................................................... 382
Clock Synchronization ............................................. 213
Clock/Instruction Cycle .............................................. 67
Comparator Output .................................................. 275
Example SPI Master Mode (CKE = 0) ..................... 387
Example SPI Master Mode (CKE = 1) ..................... 388
Example SPI Slave Mode (CKE = 0) ....................... 389
Example SPI Slave Mode (CKE = 1) ....................... 390
External Clock (All Modes except PLL) .................... 380
Fail-Safe Clock Monitor (FSCM) ................................ 39
Reading and Writing ........................................ 159
Start Condition ................................................. 229
(Case 1) ........................................................... 230
(Case 2) ........................................................... 230
Preliminary
PIC18F2XK20/4XK20
First Start Bit Timing ................................................ 221
Full-Bridge PWM Output .......................................... 178
Half-Bridge PWM Output ................................. 176, 183
High/Low-Voltage Detect Characteristics ................ 377
High/Low-Voltage Detect Operation
High/Low-Voltage Detect Operation
I
I
I
I
I
I
I
I
I
I
I
I
Internal Oscillator Switch Timing ............................... 37
Master SSP I
Master SSP I
Parallel Slave Port (PIC18F4XK20) ......................... 386
Parallel Slave Port (PSP) Read ............................... 138
Parallel Slave Port (PSP) Write ............................... 138
PWM Auto-shutdown
PWM Direction Change ........................................... 179
PWM Direction Change at Near 100% Duty Cycle .. 180
PWM Output (Active-High) ...................................... 174
PWM Output (Active-Low) ....................................... 175
Repeat Start Condition ............................................ 222
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence ............................ 252
Slave Synchronization ............................................. 197
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ........................................ 196
SPI Mode (Slave Mode, CKE = 0) ........................... 198
SPI Mode (Slave Mode, CKE = 1) ........................... 198
Synchronous Reception (Master Mode, SREN) ...... 257
Synchronous Transmission ..................................... 254
Synchronous Transmission (Through TXEN) .......... 254
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up (MCLR
Time-out Sequence on Power-up (MCLR
Time-out Sequence on Power-up (MCLR Tied
Timer0 and Timer1 External Clock .......................... 384
Timer1 Incrementing Edge ...................................... 159
Transition for Entry to Sleep Mode ............................ 44
Transition for Wake from Sleep (HSPLL) .................. 44
Transition Timing for Entry to Idle Mode .................... 45
Transition Timing for Wake from Idle to Run Mode ... 45
USART Synchronous Receive (Master/Slave) ........ 395
USART Synchronous Transmission
2
2
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 391
C Bus Start/Stop Bits ............................................ 391
C Master Mode (7 or 10-Bit Transmission) ........... 224
C Master Mode (7-Bit Reception) ......................... 225
C Slave Mode (10-Bit Reception, SEN = 0) .......... 209
C Slave Mode (10-Bit Reception, SEN = 1) .......... 215
C Slave Mode (10-Bit Transmission) .................... 210
C Slave Mode (7-bit Reception, SEN = 0) ............ 207
C Slave Mode (7-Bit Reception, SEN = 1) ............ 214
C Slave Mode (7-Bit Transmission) ...................... 208
C Slave Mode General Call Address Sequence
C Stop Condition Receive or Transmit Mode ........ 226
(VDIRMAG = 0) ............................................... 291
(VDIRMAG = 1) ............................................... 292
(7 or 10-Bit Address Mode) ............................. 216
Auto-restart Enabled ........................................ 182
Firmware Restart ............................................. 182
Timer (OST), Power-up Timer (PWRT) ........... 383
V
(MCLR Tied to V
Not Tied to V
Not Tied to V
to V
(Master/Slave) ................................................. 395
DD
DD
Rise > T
, V
2
2
C Bus Data ....................................... 393
C Bus Start/Stop Bits ........................ 393
DD
Rise < T
PWRT
DD
DD
, Case 1) ................................... 54
, Case 2) ................................... 54
DD
) ............................................ 55
) .......................................... 55
PWRT
) ............................... 54
DD
DS41303D-page 423
,